Concurrent Multi-die Optimization物理实现方案的应用

随着芯片制造工艺不断接近物理极限,使用多die堆叠的3DIC Chiplets设计已经成为延续摩尔定律的最佳途径之一。Integrity 3D-IC平台将设计规划、物理实现和系统分析统一集成于单个管理界面中,为3D设计提供了系统完善的解决方案。其中传统的die-by-die流程在3D结构建立后分别对两个die进行2D物理实现,同时工具也开发了多die协同(concurrent multidie)的物理实现流程,并行式进行多颗die的布局布线。此工作在实际项目中,使用Cadence Integrity 3D-IC工具,针对性地建立concurrent multidie的流程,将两颗die在同一个设计中实现并行摆放、3D结构单元(Hybrid Bonding bump)的位置优化、时钟树综合和绕线。协同优化的3D物理实现方案相比于die-bydie方案在设计整体结果上有更好的表现。

Contact resistance asymmetry of amorphous indium–gallium–zinc–oxide thin-film transistors by scanning Kelvin probe microscopy

In this work, a method based on scanning Kelvin probe microscopy is proposed to separately extract source/drain（S/D） series resistance in operating amorphous indium–gallium–zinc–oxide（a-IGZO） thin-film transistors. The asymmetry behavior of S/D contact resistance is deduced and the underlying physics is discussed. The present results suggest that the asymmetry of S/D contact resistance is caused by the difference in bias conditions of the Schottky-like junction at the contact interface induced by the parasitic reaction between contact metal and a-IGZO. The overall contact resistance should be determined by both the bulk channel resistance of the contact region and the interface properties of the metalsemiconductor junction.

Temperature-dependent bias-stress-induced electrical instability of amorphous indium-gallium-zinc-oxide thin-film transistors

The time and temperature dependence of threshold voltage shift under positive-bias stress（PBS） and the following recovery process are investigated in amorphous indium-gallium-zinc-oxide（a-IGZO） thin-film transistors. It is found that the time dependence of threshold voltage shift can be well described by a stretched exponential equation in which the time constant τ is found to be temperature dependent. Based on Arrhenius plots, an average effective energy barrier Eτ stress= 0.72 eV for the PBS process and an average effective energy barrier Eτ recovery= 0.58 eV for the recovery process are extracted respectively. A charge trapping/detrapping model is used to explain the threshold voltage shift in both the PBS and the recovery process. The influence of gate bias stress on transistor performance is one of the most critical issues for practical device development.

基于Innovus工具的IR Drop自动化修复

在先进工艺节点下,芯片电源网络的电阻增加和高密度的晶体管同时翻转会在VDD和VSS上产生电压降(IR Drop),导致芯片产生时序问题和功能性障碍。采用基于Innovus工具的三种自动化IR Drop修复流程在PR(Placement and Route)阶段优化模块的动态IR Drop。结果表明,Pegasus PG Fix Flow和IR-Aware Placement这两种方法能分别修复设计的48%和33.8%的IR Drop违例,且不会恶化时序和DRC(Design Rule Check),而IR-Aware PG Strape Addition这种方法的优化力度相对较小,且会使DRC有较大程度的恶化。

The Effect of Oxygen Partial Pressure during Active Layer Deposition on Bias Stability of a-InGaZnO TFTs

The effect of oxygen partial pressure （Po2） during the channel layer deposition on bias stability of amorphous indium-gallium-zinc oxide （a-IGZO） thin film transistors （TFTs） is investigated. As Po2 increases from 10% to 30%, it is found that the device shows enhanced bias stress stability with significantly reduced threshold voltage drift under positive gate bias stress. Based on the x-ray photoelectron spectroscopy measurement, the concentration of oxygen vacancies （Or） within the a-IGZO layer is suppressed by increasing Po2. Meanwhile, the low-frequency noise analysis indicates that the average trap density near the channel/dielectric interface continuously drops with increasing Po2. Therefore, the improved interface quality with increasing Po2 during the channel layer deposition can be attributed to the reduction of interface Ov-related defects, which agrees with the enhanced bias stress stability of the a-IGZO TFTs.

Investigation and active suppression of self-heating induced degradation in amorphous InGaZnO thin film transistors

Self-heating effect in amorphous InGaZnO thin-film transistors remains a critical issue that degrades device performance and stability, hindering their wider applications. In this work, pulsed current–voltage analysis has been applied to explore the physics origin of self-heating induced degradation, where Joule heat is shortly accumulated by drain current and dissipated in repeated time cycles as a function of gate bias. Enhanced positive threshold voltage shift is observed at reduced heat dissipation time, higher drain current, and increased gate width. A physical picture of Joule heating assisted charge trapping process has been proposed and then verified with pulsed negative gate bias stressing scheme, which could evidently counteract the self-heating effect through the electric-field assisted detrapping process. As a result, this pulsed gate bias scheme with negative quiescent voltage could be used as a possible way to actively suppress self-heating related device degradation.

Influence of white light illumination on the performance of a-IGZO thin film transistor under positive gate-bias stress

The influence of white light illumination on the stability of an amorphous In GaZnO thin film transistor is investigated in this work. Under prolonged positive gate bias stress, the device illuminated by white light exhibits smaller positive threshold voltage shift than the device stressed under dark. There are simultaneous degradations of field-effect mobility for both stressed devices, which follows a similar trend to that of the threshold voltage shift. The reduced threshold voltage shift under illumination is explained by a competition between bias-induced interface carrier trapping effect and photon-induced carrier detrapping effect. It is further found that white light illumination could even excite and release trapped carriers originally exiting at the device interface before positive gate bias stress, so that the threshold voltage could recover to an even lower value than that in an equilibrium state. The effect of photo-excitation of oxygen vacancies within the a-IGZO film is also discussed.

Impact of Interfacial Trap Density of States on the Stability of Amorphous InGaZnO-Based Thin-Film Transistors

The impact of interfacial trap states on the stability of amorphous indium-gallium-zinc oxide thin film transistors is studied under positive gate bias stress.With increasing stress time,the device exhibits a large positive drift of threshold voltage while maintaining a stable sub-threshold swing and a constant field-effect mobility of channel electrons.The threshold voltage drift is explained by charge trapping at the high-density trap states near the channel/dielectric interface,which is confirmed by photo-excited charge-collection spectroscopy measurement.

Frequency Performance of Ring Oscillators Based on a-IGZO Thin-Film Transistors

Ring oscillators based on indium gallium zinc oxide thin film transistors are fabricated on glass substrates. The oscillator circuit consists of seven delay stages and an output buffer inverter. The element inverter exhibits a voltage gain higher than -6 V/V and a wide output swing close to 85% of the full swing range. The dynamic performance of the ring oscillators is evaluated as a function of supply voltage and at different gate lengths. A maximum oscillation frequency of 0.88MHz is obtained for a supply voltage of 50V, corresponding to a propagation delay of less than 85 ns/stage.