This paper presents a fully integrated passive UHF RFID tag chip complying with the ISO18000-6B protocol.The tag chip includes an RF/analog front-end,a baseband processor,and a 512-bit EEPROM memory.To improve power c...This paper presents a fully integrated passive UHF RFID tag chip complying with the ISO18000-6B protocol.The tag chip includes an RF/analog front-end,a baseband processor,and a 512-bit EEPROM memory.To improve power conversion efficiency,a Schottky barrier diode based rectifier is adopted.A novel voltage reference using the peaking current source is discussed in detail,which can meet the low-power,low-voltage requirement while retaining circuit simplicity.Most of the analog blocks are designed to work under sub-1 V to reduce power consumption,and several practical methods are used to further reduce the power consumption of the baseband processor.The whole tag chip is implemented in a TSMC 0.18μm CMOS process with a die size of 800×800μm;. Measurement results show that the total power consumption of the tag chip is only 7.4μW with a sensitivity of -12 dBm.展开更多
This paper presents a passive UHF RFID tag with a dynamicVthcancellation （DVC） rectifier. In the rectifier, the threshold voltages of MOSFETs are cancelled by applying gate bias voltages, which are dynamically chang...This paper presents a passive UHF RFID tag with a dynamicVthcancellation （DVC） rectifier. In the rectifier, the threshold voltages of MOSFETs are cancelled by applying gate bias voltages, which are dynamically changed according to the states of the MOSFETs. The DVC rectifier enables both low ONresistance and small re verse leakage of the MOSFETs, resulting in high power conversion efficiency （PCE）. An areaefficient demodulator with a novel average detector is also designed, which takes advantage of the rectifier＇s first stage as the envelope detector. The whole tag chip is implemented in a 0.18 μm CMOS process with a die size of 880 x 950μm2. Measurement results show that the rectifier achieves a maximum PCE of 53.7% with 80 kΩ resistor load.展开更多
This paper presents a voltage regulator system for passive UHF RFID transponders, which contains a rectifier, a limiter, and a regulator. The rectifier achieves power by rectifying the incoming RF energy. Due to the h...This paper presents a voltage regulator system for passive UHF RFID transponders, which contains a rectifier, a limiter, and a regulator. The rectifier achieves power by rectifying the incoming RF energy. Due to the huge variation of the rectified voltage, a limiter at the rectifier output is used to clamp the rectified voltage. In this paper, the design of a limiter circuit is discussed in detail, which can provide a stable limiting voltage with low sensitivity to temperature variation and process dispersion. The key aspect of the voltage regulator system is the dynamic bandwidth boosting in the regulator. By sensing the excess current that is bypassed in the limiter during periods of excess energy, the bias current as well as the bandwidth of the regulator are increased, the output supply voltage can recover quickly from line transients during the periods of no RF energy to a full blast of RF energy. This voltage regulator system is implemented in a 0.18μm CMOS process.展开更多
A fully integrated passive UHF RFID tag complying with the ISO 18000-6B protocol is presented, which includes an analog front-end, a baseband processor, and an EEPROM memory. To extend the communication range, a high ...A fully integrated passive UHF RFID tag complying with the ISO 18000-6B protocol is presented, which includes an analog front-end, a baseband processor, and an EEPROM memory. To extend the communication range, a high efficiency differential-drive CMOS rectifier is adopted. A novel high performance voltage limiter is used to provide a stable limiting voltage, with a 172 mV voltage variation against temperature variation and process dispersion. The dynamic band-enhancement technique is used in the regulator circuit to improve the regulating capacity. A rail-to-rail hysteresis comparator is adopted to demodulate the signal correctly in any condition. The whole transponder chip is implemented in a 0.18μm CMOS process, with a die size of 900 × 800 μm2. Our measurement results show that the total power consumption of the tag chip is only 6.8 μW, with a sensitivity of -13.5 dBm.展开更多
基金supported by the Shenzhen Key Laboratory Development Project,China(No.CXB201104210007A)
文摘This paper presents a fully integrated passive UHF RFID tag chip complying with the ISO18000-6B protocol.The tag chip includes an RF/analog front-end,a baseband processor,and a 512-bit EEPROM memory.To improve power conversion efficiency,a Schottky barrier diode based rectifier is adopted.A novel voltage reference using the peaking current source is discussed in detail,which can meet the low-power,low-voltage requirement while retaining circuit simplicity.Most of the analog blocks are designed to work under sub-1 V to reduce power consumption,and several practical methods are used to further reduce the power consumption of the baseband processor.The whole tag chip is implemented in a TSMC 0.18μm CMOS process with a die size of 800×800μm;. Measurement results show that the total power consumption of the tag chip is only 7.4μW with a sensitivity of -12 dBm.
文摘This paper presents a passive UHF RFID tag with a dynamicVthcancellation （DVC） rectifier. In the rectifier, the threshold voltages of MOSFETs are cancelled by applying gate bias voltages, which are dynamically changed according to the states of the MOSFETs. The DVC rectifier enables both low ONresistance and small re verse leakage of the MOSFETs, resulting in high power conversion efficiency （PCE）. An areaefficient demodulator with a novel average detector is also designed, which takes advantage of the rectifier＇s first stage as the envelope detector. The whole tag chip is implemented in a 0.18 μm CMOS process with a die size of 880 x 950μm2. Measurement results show that the rectifier achieves a maximum PCE of 53.7% with 80 kΩ resistor load.
基金supported by the Shenzhen Key Laboratory Development Project,China(No.CXB201104210007A)
文摘This paper presents a voltage regulator system for passive UHF RFID transponders, which contains a rectifier, a limiter, and a regulator. The rectifier achieves power by rectifying the incoming RF energy. Due to the huge variation of the rectified voltage, a limiter at the rectifier output is used to clamp the rectified voltage. In this paper, the design of a limiter circuit is discussed in detail, which can provide a stable limiting voltage with low sensitivity to temperature variation and process dispersion. The key aspect of the voltage regulator system is the dynamic bandwidth boosting in the regulator. By sensing the excess current that is bypassed in the limiter during periods of excess energy, the bias current as well as the bandwidth of the regulator are increased, the output supply voltage can recover quickly from line transients during the periods of no RF energy to a full blast of RF energy. This voltage regulator system is implemented in a 0.18μm CMOS process.
文摘A fully integrated passive UHF RFID tag complying with the ISO 18000-6B protocol is presented, which includes an analog front-end, a baseband processor, and an EEPROM memory. To extend the communication range, a high efficiency differential-drive CMOS rectifier is adopted. A novel high performance voltage limiter is used to provide a stable limiting voltage, with a 172 mV voltage variation against temperature variation and process dispersion. The dynamic band-enhancement technique is used in the regulator circuit to improve the regulating capacity. A rail-to-rail hysteresis comparator is adopted to demodulate the signal correctly in any condition. The whole transponder chip is implemented in a 0.18μm CMOS process, with a die size of 900 × 800 μm2. Our measurement results show that the total power consumption of the tag chip is only 6.8 μW, with a sensitivity of -13.5 dBm.
