A 14 bit 51.2 kS/s extended counting analog to digital converter （EC-ADC） is presented. Two techniques are utilized to reduce its power consumption. First, a double-sampling configuration based on a fully-floating b...A 14 bit 51.2 kS/s extended counting analog to digital converter （EC-ADC） is presented. Two techniques are utilized to reduce its power consumption. First, a double-sampling configuration based on a fully-floating bilin- ear integrator is proposed to reduce the clock frequency. Second, a class-AB operational transconductance amplifier （OTA） is designed to improve the power efficiency. In addition, the chopping technique is used to eliminate the OTA flicker noise effect. The proposed ADC is fabricated in 0.18 μm CMOS technology with a core area of 0.04 mm2. At a 51.2 kS/s conversion rate, it achieves a 94 dB SFDR and an 11.6 bit ENOB, while consuming only 77 μW from a 1.8 V power supply. The figure of merit is only 0.48 p J/step.展开更多
基金supported by the National High Technology Research and Development Program of China(No.2009AA042321)
文摘A 14 bit 51.2 kS/s extended counting analog to digital converter （EC-ADC） is presented. Two techniques are utilized to reduce its power consumption. First, a double-sampling configuration based on a fully-floating bilin- ear integrator is proposed to reduce the clock frequency. Second, a class-AB operational transconductance amplifier （OTA） is designed to improve the power efficiency. In addition, the chopping technique is used to eliminate the OTA flicker noise effect. The proposed ADC is fabricated in 0.18 μm CMOS technology with a core area of 0.04 mm2. At a 51.2 kS/s conversion rate, it achieves a 94 dB SFDR and an 11.6 bit ENOB, while consuming only 77 μW from a 1.8 V power supply. The figure of merit is only 0.48 p J/step.
