The development of IoT(Internet of Things)calls for circuit designs with energy and area efficiency for edge devices.Approximate computing which trades unnecessary computation precision for hardware cost savings is a ...The development of IoT(Internet of Things)calls for circuit designs with energy and area efficiency for edge devices.Approximate computing which trades unnecessary computation precision for hardware cost savings is a promising direction for error-tolerant applications.Multipliers,as frequently invoked basic modules which consume non-trivial hardware costs,have been introduced approximation to achieve distinct energy and area savings for data-intensive applications.In this paper,we propose a fixed-point approximate multiplier that employs a linear mapping technique,which enables the configurability of approximation levels and the unbiasedness of computation errors.We then introduce a dynamic truncation method into the proposed multiplier design to cover a wider and more fine-grained configuration range of approximation for more flexible hardware cost savings.In addition,a novel normalization module is proposed for the required shifting operations,which balances the occupied area and the critical path delay compared with normal shifters.The introduced errors of our proposed design are analyzed and expressed by formulas which are validated by experimental results.Experimental evaluations show that compared with accurate multipliers,our proposed approximate multiplier design provides maximum area and power savings up to 49.70%and 66.39%respectively with acceptable computation errors.展开更多
基金supported by the National Key Research and Development Program of China under Grant No.2018YFE0126300the National Natural Science Foundation of China under Grant Nos.62034007,62141404.
文摘The development of IoT(Internet of Things)calls for circuit designs with energy and area efficiency for edge devices.Approximate computing which trades unnecessary computation precision for hardware cost savings is a promising direction for error-tolerant applications.Multipliers,as frequently invoked basic modules which consume non-trivial hardware costs,have been introduced approximation to achieve distinct energy and area savings for data-intensive applications.In this paper,we propose a fixed-point approximate multiplier that employs a linear mapping technique,which enables the configurability of approximation levels and the unbiasedness of computation errors.We then introduce a dynamic truncation method into the proposed multiplier design to cover a wider and more fine-grained configuration range of approximation for more flexible hardware cost savings.In addition,a novel normalization module is proposed for the required shifting operations,which balances the occupied area and the critical path delay compared with normal shifters.The introduced errors of our proposed design are analyzed and expressed by formulas which are validated by experimental results.Experimental evaluations show that compared with accurate multipliers,our proposed approximate multiplier design provides maximum area and power savings up to 49.70%and 66.39%respectively with acceptable computation errors.
