碳膜保护对高温激活SiC表面形貌的影响

采用碳膜覆盖于SiC晶片表面,作为SiC离子注入后高温激活退火的保护层,1650℃20 min高温退火后,有碳膜保护的SiC晶片表面粗糙度RMS只有0.6 nm,无明显形貌退化。AZ5214光刻胶在不同温度条件Ar气氛围下碳化40 min,光刻胶均转变为纳米晶体石墨化碳膜。进行Raman测试表明,碳膜D峰和G峰的比值随碳化温度升高而增大,800℃高温碳化形成的碳膜ID:IG达到3.57,对高温激活退火SiC表面保护效果最佳,经过Ar气氛围下1 650℃20 min激活退火后,有碳膜保护和无碳膜保护的SiC表面粗糙度RMS分别为0.6 nm和3.6 nm。

1200V SiC MOSFET晶体管的高温可靠性研究

高温可靠性是目前限制SiC MOSFET晶体管高温应用的关键问题之一。本文介绍了基于国内碳化硅器件工艺平台研制的1 200 V SiC MOSFET器件的直流特性,并通过高温栅偏(HTGB)和高温反偏(HTRB)试验对器件高温可靠性进行测试分析。试验结果表明:所研制的1 200 V SiC MOSFET器件在经过168 h的HTGB和HTRB可靠性试验后,所有测试器件的击穿电压>1 200 V,阈值电压偏移量<15%,导通电阻偏移量<15%,显示出优良的器件鲁棒性,也初步证明了国产SiC MOSFET器件的设计、工艺及其研制的可行性。

1200 V/100 A高温大电流4H-SiC JBS器件的研制

基于SiC结势垒肖特基（JBS）二极管工作原理及其电流/电场均衡分布理论,采用高温大电流单芯片设计技术及大尺寸芯片加工技术,研制了1 200 V/100 A高温大电流4H-SiC JBS二极管。该器件采用优化的材料结构、有源区结构和终端结构,有效提高了器件的载流子输运能力。测试结果表明,当正向导通压降为1.60 V时,其正向电流密度达247 A/cm^2（以芯片面积计算）。在测试温度25和200℃时,当正向电流为100 A时,正向导通压降分别为1.64和2.50 V;当反向电压为1 200 V时,反向漏电流分别小于50和200μA。动态特性测试结果表明,器件的反向恢复特性良好。器件均通过100次温度循环、168 h的高温高湿高反偏（H3TRB）和高温反偏可靠性试验,显示出优良的鲁棒性。器件的成品率达70%以上。

Influences of high-temperature annealing on atomic layer deposited Al_2O_3/4H-SiC

High-temperature annealing of the atomic layer deposition （ALD） of Al2O3 films on 4H-SiC in O 2 atmosphere is studied with temperature ranging from 800℃ to 1000℃. It is observed that the surface morphology of Al2O3 films annealed at 800℃ and 900℃ is pretty good, while the surface of the sample annealed at 1000℃ becomes bumpy. Grazing incidence X-ray diffraction （GIXRD） measurements demonstrate that the as-grown films are amorphous and begin to crystallize at 900℃. Furthermore, C–V measurements exhibit improved interface characterization after annealing, especially for samples annealed at 900℃ and 1000℃. It is indicated that high-temperature annealing in O2 atmosphere can improve the interface of Al2O3 /SiC and annealing at 900℃ would be an optimum condition for surface morphology, dielectric quality, and interface states.

Annealing temperature influence on the degree of inhomogeneity of the Schottky barrier in Ti/4H–SiC contacts

Tung＇s model was used to analyze anomalies observed in Ti/Si C Schottky contacts. The degree of the inhomogeneous Schottky barrier after annealing at different temperatures is characterized by the ‘T0anomaly＇ and the difference（△Φ）between the uniformly high barrier height（Φ0B） and the effective barrier height（Φeff B）. Those two parameters of Ti Schottky contacts on 4H–Si C were deduced from I–V measurements in the temperature range of 298 K–503 K. The increase in Schottky barrier（SB） height（ΦB） and decrease in the ideality factor（n） with an increase measurement temperature indicate the presence of an inhomogeneous SB. The degree of inhomogeneity of the Schottky barrier depends on the annealing temperature, and it is at its lowest for 500-°C thermal treatment. The degree of inhomogeneity of the SB could reveal effects of thermal treatments on Schottky contacts in other aspects.

SiO2/4H-SiC界面氮化退火

通过1 300℃高温干氧热氧化法在n型4H-SiC外延片上生长了厚度为60 nm的SiO2栅氧化层。为了开发适合于生长低界面态密度和高沟道载流子迁移率的SiC MOSFET器件产品的栅极氧化层退火条件,研究了不同退火条件下的SiO2/SiC界面电学特性参数。制作了MOS电容和横向MOSFET器件,通过表征SiO2栅氧化层C-V特性和MOSFET器件I-V特性,提取平带电压、C-V磁滞电压、SiO2/SiC界面态密度和载流子沟道迁移率等电学参数。实验结果表明,干氧氧化形成SiO2栅氧化层后,在1 300℃通入N2退火30 min,随后在相同温度下进行NO退火120 min,为最佳栅极氧化层退火条件,此时,SiO2/SiC界面态密度能够降低至2.07×1012cm-2·e V^(-1)@0.2 e V,SiC MOSFET沟道载流子迁移率达到17 cm2·V^(-1)·s^(-1)。

Fabrication and Characterization of 1700 V 4H-SiC Vertical Double-Implanted Metal-Oxide-Semiconductor Field-Effect Transistors

The fabrication and characterization of 1700 V 7 A 4H-SiC vertical double-implanted metal-oxide-semiconductor field-effect transistors （VDMOSFETs） are reported. The drift layer is 17μm in thickness with 5 × 10^15 cm^-3 n-type doping, and the channel length is 1μm. The MOSFETs show a peak mobility of 17cm2/V.s and a typical threshold voltage of 3 V. The active area of 0.028cm2 delivers a forward drain current of 7A at Vcs = 22 V and VDS= 15 V. The specific on-resistance （Ron,sv） is 18mΩ.cm2 at VGS= 22 V and the blocking voltage is 1975 V （IDS 〈 lOOnA） at VGS = 0 V.

Charge trapping behavior and its origin in Al_2O_3/SiC MIS system

Charge trapping behavior and its origin in Al2O3/SiC MOS structure are investigated by analyzing the capacitance–voltage(C–V) hysteresis and the chemical composition of the interface. The C–V hysteresis is measured as a function of oxide thickness series for an Al2O3/SiC MIS capacitor. The distribution of the trapped charges, extracted from the C–V curves, is found to mainly follow a sheet charge model rather than a bulk charge model. Therefore, the electron injection phenomenon is evaluated by using linear fitting. It is found that most of the trapped charges are not distributed exactly at the interface but are located in the bulk of the Al2O3 layers, especially close to the border. Furthermore, there is no detectable oxide interface layer in the x-ray photoelectron spectroscope(XPS) and transmission electron microscope(TEM)measurements. In addition, Rutherford back scattering(RBS) analysis shows that the width of the Al2O3/SiC interface is less than 1 nm. It could be concluded that the charge trapping sites in Al2O3/SiC structure might mainly originate from the border traps in Al2O3 film rather than the interface traps in the interfacial transition layer.

高品质因数SiC PiN二极管的研制

基于Silvaco仿真得到3 300 V SiC PiN二极管器件优化结构,开展了SiC刻蚀工艺和欧姆接触工艺研发,制备出具有倾角为48°的缓变台面结构和比接触电阻率在10-5Ω·cm^2量级的欧姆接触的SiC PiN二极管。所研制出的PiN器件最高反向阻断能力达到4 000 V,在100 A/cm^2的正向电流密度下正向导通压降为3.4 V。该器件的品质因数(FOM)达到2 461 MW/cm^2,目前在国内处于领先水平。

Characterization of the effects of nitrogen and hydrogen passivation on SiO2/4H-SiC interface by low temperature conductance measurements

We investigate the effects of NO annealing and forming gas （FG） annealing on the electrical properties of a SiO2/SiC interface by low-temperature conductance measurements. With nitrogen passivation, the density of interface states （DIT） is significantly reduced in the entire energy range, and the shift of flatband voltage, AVFB, is effectively suppressed to less than 0.4 V. However, very fast states are observed after NO annealing and the response frequencies are higher than 1 MHz at room temperature. After additional FG annealing, the DIT and AVFB are further reduced. The values of the DIT decrease to less than 1011 cm-2 eV- 1 for the energy range of Ec - ET 〉/0.4 eV. It is suggested that the fast states in shallow energy levels originated from the N atoms accumulating at the interface by NO annealing. Though FG annealing has a limited effect on these shallow traps, hydrogen can terminate the residual Si and C dangling bonds corresponding to traps at deep energy levels and improve the interface quality further. It is indicated that NO annealing in conjunction with FG annealing will be a better post-oxidation process method for high performance SiC MOSFETs.

Improved adhesion and interface ohmic contact on n-type 4H-SiC substrate by using Ni/Ti/Ni

The Ni/Ti/Ni multilayer ohmic contact properties on a 4H-SiC substrate and improved adhesion with the Ti/Au overlayer have been investigated. The best specific contact resistivity of 3.16 × 10^-5 Ω.cm^2 was obtained at 1050 ℃. Compared with Ni/SiC ohmic contact, the adhesion between Ni/Ti/Ni/SiC and the Ti/Au overlayer was greatly improved and the physical mechanism under this behavior was analyzed by using Raman spectroscopy and X-ray energy dispersive spectroscopy （EDS） measurement. It is shown that a Ti-carbide and Ni-silicide compound exist at the surface and there is no graphitic carbon at the surface of the Ni/Ti/Ni structure by Raman spectroscopy, while a large amount of graphitic carbon appears at the surface of the Ni/SiC structure, which results in its bad adhesion. Moreover, the interface of the Ni/Ti/Ni/SiC is improved compared to the interface of Ni/SiC.