Ni/4H-SiC肖特基二极管高温特性研究

采用自行研制的工作在800℃的半导体器件高温测试装置,对Ni/4H SiC肖特基二极管的伏安特性在常温297K至677K的温度范围内进行了测量,表明温度升高对正向特性的影响非常显著,而对较低偏置(30V以下)条件下的反向特性影响则比较小.对实验结果进行了比较分析,I V特性测量说明镍4H SiC肖特基二极管有较好的整流特性,在正向偏压条件下,热电子发射是其主要的输运机理,理想因子在297～677K的温度范围内从1 165增加到1 872,肖特基势垒高度的变化范围为0 916～2 117eV,正向导通电压为0 5V.

4H-SiC肖特基二极管γ射线探测器的模型与分析

在研究反偏压4H-SiC肖特基二极管作为γ射线探测器工作机理的基础上建立了数值模型,模拟了不同偏压和辐照剂量率下探测器的暗电流、工作电流和灵敏度。模拟结果表明:探测器的灵敏度随反向偏压的增加而上升;对于Au/SiC肖特基二极管,有源区掺杂数密度为2.2×1015cm-3时,0 V偏压下探测器的灵敏度为13.9×10-9C/Gy,100 V偏压下为24.5×10-9C/Gy。计算结果与实验数据符合得较好。

Al掺杂4H-SiC同质外延的缓冲层

利用扫描电子显微镜(SEM)、X射线双晶衍射谱(XRD)和光致发光谱(PL)对在4H-SiC单晶衬底上采用CVD同质外延的4H-SiC单晶薄膜的特性进行研究,发现外延层有很好的晶格结构和完整性。由于Al原位掺杂引起的晶格失配和衬底和外延的晶向偏离,在样品的衬底和外延的界面出现了约1μm的缓冲层,使得XRD摇摆曲线距主峰左侧约41arcs出现了强衍射峰。缓冲层中存在大量的堆垛缺陷和位错,引入缺陷能级,使室温PL测试为"绿带"发光。通过PL全片扫描发现缓冲层在整个样品中普遍存在且分布均匀。

陷阱效应对4H-SiC MESFET温度特性的影响

针对4H-SiC射频MESFET中的自热效应,建立了基于解析模型的材料参数温度模型和器件直流模型.研究了由陷阱造成的背栅效应,并结合材料的温度特性分析了温度升高对器件特性的影响.分析了陷阱对器件特性的影响,并进一步阐明了陷落-发射机制.计算得到陷阱能级为1.07eV,俘获截面为1×10-8cm2,器件的自升温达到100K以上,能够较好地反映实验结果.分析结果表明,背栅电势随陷阱浓度的增大而增大,并随着漏极电压的增大而减小,在室温下达到～3V.另外,由于器件中存在自热效应,背栅电势随漏压的变化加剧.这些模拟分析对实际器件的设计及工艺制造提供了理论上的依据.

陷阱效应对4H-SiC MESFET频率特性的影响

针对4H-SiC射频MESFET中的陷阱效应,建立了基于解析模型的器件小信号参数模型,引入能够反映陷阱影响的参数Rds″、gm″、Css等,从而能够由此分析器件特性随频率偏移的情况.对沟道缓冲层界面深能级陷阱的分析表明,4H-SiC MESFET的跨导既有正向偏移,也有负向偏移.偏移频率在室温下不足1Hz,但在600K的温度下则可达到MHz的量级.结合自热效应模型,论文还分析了栅、漏极偏置和温度对器件频率偏移特性的影响.模拟结果表明,随着温度的上升,偏移频段上升.本文的模拟分析对器件的设计提供了理论上的依据.

零偏4H-SiC衬底的同质外延方法

基于水平热壁化学气相沉积(CVD)技术,采用原位刻蚀方法,在3英寸(1英寸=2.54 cm)(0001)Si面零偏4H-SiC衬底上生长了高质量的同质外延层,并对其主要工艺参数和生长机制进行了探讨。利用微分干涉相差显微镜、喇曼散射及湿法腐蚀等表征手法对样品进行了测试分析。测量结果表明,4H-SiC占整个外延表面积的99%以上,此外,该工艺消除了4H-SiC同质外延层中的基面位错,提高了外延层的质量。同时对零偏4H-SiC衬底的同质外延的工艺过程和理论进行了研究和讨论,实验发现,生长前的原位刻蚀、初始生长参数、碳硅原子比以及生长温度对于维持外延层晶型、避免3C-SiC多型的产生具有重要影响。

4H-SiC MESFET的新型经验电容模型

基于器件工作机理,提出了一种新型的4H-SiC MESFET经验大信号电容模型。模型参数提取采用Lev-enberg-Marquardt优化算法,提取的模型主要参数具有一定物理意义。C-V特性的模型模拟结果与实验数据的比较表明两者符合良好。该模型还与CAD工具的通用电容模型进行了比较,结果表明新模型具有更高的精度。

钒掺杂形成半绝缘6H-SiC的补偿机理(英文)

研究了钒掺杂生长半绝缘6 H-SiC的补偿机理.二次离子质谱分析结果表明,非故意掺杂生长的6 H-SiC中,氮是主要的剩余浅施主杂质.通过较深的钒受主能级对氮施主的补偿作用,得到了具有半绝缘特性的SiC材料.借助电子顺磁共振和吸收光谱分析,发现SiC中同时存在中性钒( V4 +)和受主态钒( V3 +)的电荷态,表明掺入的部分杂质钒通过补偿浅施主杂质氮,形成受主态钒,这与二次离子质谱分析结果相吻合.通过对样品进行吸收光谱和低温光致发光测量,发现钒受主能级在6 H-SiC中位于导带下0.62eV处.

一种用于非线性分析的新型4H-SiC MESFET大信号经验模型(英文)

提出了一种简洁的新型4H-SiC MESFET经验大信号模型.在Materka漏电流模型基础上,改进了沟道调制因子和饱和电压系数的建模方式,电容模型采用了改进的电荷守恒模型.参数的提取和优化采用了Levenberg-Marquardt优化方法.在偏置点VDS=20V,IDS=80mA和工作频率1.8GHz下,模型直流电流-电压扫描曲线、输出功率、功率附加效率和增益的模拟结果与实验数据符合良好.

高能量钒注入n型4H-SiC的欧姆接触形成(英文)

借助二次离子质谱法分析了注入的钒离子在碳化硅中的分布.即使经过1650℃的高温退火,钒在碳化硅中的再扩散也不显著.退火并没有导致明显的钒向碳化硅表面扩散形成堆积的现象,由于缺少钒的补偿作用,表面薄层的自由载流子浓度保持不变.采用线性传输线模型测量了钒注入n型4H-SiC上的Ni基接触电阻,在1050℃下,在氮、氢混合气体中退火10min,形成的最低比接触电阻为4.4×10-3Ω.cm2.金属化退火后的XRD分析结果表明,镍、碳化硅界面处形成了Ni2Si和石墨相.观测到的石墨相是由于退火导致C原子外扩散并堆积形成,同时在碳化硅表面形成C空位.C空位可以提高有效载流子浓度,降低势垒高度并减小耗尽层宽度,对最终形成欧姆接触起到了关键作用.

Si衬底上3C-SiC异质外延应力的消除

利用低压化学气相沉积方法在N型Si衬底上异质外延生长3C-SiC薄膜,研究和分析了不同碳化工艺和生长工艺对3C-SiC外延层的影响;探讨了Si衬底3C-SiC异质外延应力的消除机理。通过台阶仪和XRD对不同工艺条件下的外延层质量进行分析,得到最佳工艺条件的碳化温度为1 000℃,碳化时间为5 min,生长温度为1 200℃,生长速度为4μm/h。对最佳工艺条件下得到的外延层的台阶仪分析表明外延层弯曲度仅为5μm/45 mm;而外延层的XRD和AFM分析表明,3μm厚度外延层SiC(111)半高宽为0.15°,表面粗糙度为15.4nm,表明外延层结晶质量良好。

钒受主能级在n型4H-SiC中的深能级瞬态傅里叶谱和光致发光(英文)

借助深能级瞬态傅里叶谱研究了钒离子注入在SiC中引入的深能级陷阱.掺入的钒在4 H-SiC中形成两个深受主能级,分别位于导带下0.81和1.02eV处,其电子俘获截面分别为7.0×10-16和6.0×10-16cm2.对钒离子注入4 H-SiC样品进行低温光致发光测量,同样发现两个电子陷阱,分别位于导带下0.80和1.16eV处。结果表明,在n型4 H-SiC掺入杂质钒可以同时形成两个深的钒受主能级,分别位于导带下0.8±0.01和1.1±0.08eV处.

Al/Ti/4H-SiC Schottky barrier diodes with inhomogeneous barrier heights

This paper investigates the current-voltage （I-V） characteristics of Al/Ti/4H-SiC Schottky barrier diodes （SBDs） in the temperature range of 77 K-500 K, which shows that Al/Ti/4H SiC SBDs have good rectifying behaviour. An abnormal behaviour, in which the zero bias barrier height decreases while the ideality factor increases with decreasing temperature （T）, has been successfully interpreted by using thermionic emission theory with Gaussian distribution of the barrier heights due to the inhomogeneous barrier height at the A1/Ti/4H-SiC interface. The effective Richardson constant A＊ = 154 A/cm2 . K2 is determined by means of a modified Richardson plot In（I0/T2） - （qσ）2/2（κT）2 versus q/kT, which is very close to the theoretical value 146 A/cm2 · K2.

SiC epitaxial layers grown by chemical vapour deposition and the fabrication of Schottky barrier diodes

This paper presents the results of unintentionally doped 4H-SiC epilayers grown on n-type Si-faced 4H-SiC substrates with 8° off-axis toward the [1120] direction by low pressure horizontal hot-wall chemical vapour deposition. Growth temperature and pressure are 1580 ℃ and 10^4 Pa, respectively. Good surface morphology of the sample is observed using atomic force microscopy （AFM） and scanning electron microscopy （SEM）. Fourier transform infrared spectroscopy （FTIR） and x-ray diffraction （XRD） are used to characterize epitaxial layer thickness and the structural quality of the films respectively. The carrier concentration in the unintentional 4H-SiC homoepitaxial layer is about 6.4×10^14 cm^-3 obtained by C-V measurements. Schottky barrier diodes （SBDs） are fabricated on the epitaxial wafer in order to verify the quality of the wafer and to obtain information about the correlation between background impurity and electrical properties of the devices. Ni and Ti/4H-SiC Schottky barrier diodes with very good performances were obtained and their ideality factors are 1.10 and 1.05 respectively.

A CAD oriented quasi-analytical large-signal drain current model for 4H-SiC MESFETs

This paper reports that a 4H-SiC MESFET （Metal Semiconductor Field Effect Transistor） large signal drain current model based on physical expressions has been developed to be used in CAD tools. The form of drain current model is based on semi-empirical MESFET model, and all parameters in this model are determined by physical parameters of 4H-SiC MESFET. The verification of the present model embedded in CAD tools is made, which shows a good agreement with measured data of large signal DC I-V characteristics, PAE （power added efficiency）, output power and gain.

Edge termination study and fabrication of a 4H-SiC junction barrier Schottky diode

The 4H-SiC junction barrier Schottky （JBS） diodes terminated by field guard rings and offset field plate are designed, fabricated and characterized. It is shown experimentally that a 3-μm P-type implantation window spacing gives an optimum trade-off between forward drop voltage and leakage current density for these diodes, yielding a specific on-resistance of 8.3 mΩ-cm2. A JBS diode with a turn-on voltage of 0.65 V and a reverse current density less than 1 A/cm2 under 500 V is fabricated, and the reverse recovery time is tested to be 80 ns, and the peak reverse current is 28.1 mA. Temperature-dependent characteristics are also studied in a temperature range of 75 °C-200 °C. The diode shows a stable Schottky barrier height of up to 200°C and a stable operation under a continuous forward current of 100 A/cm2.

Temperature-dependent characteristics of 4H-SiC junction barrier Schottky diodes

The current-voltage characteristics of 4H-SiC junction barrier Schottky （JBS） diodes terminated by an offset field plate have been measured in the temperature range of 25-300℃. An experimental barrier height value of about 0.5 eV is obtained for the Ti/4H-SiC JBS diodes at room temperature. A decrease in the experimental barrier height and an increase in the ideality factor with decreasing temperature are shown. Reverse recovery testing also shows the temperature dependence of the peak recovery current density and the reverse recovery time. Finally, a discussion of reducing the reverse recovery time is presented.

Fabrications and characterizations of high performance 1.2 kV,3.3 kV, and 5.0 kV class 4H–SiC power SBDs

In this paper, 1.2 kV, 3.3 kV, and 5.0 kV class 4H-SiC power Schottky barrier diodes （SBDs） are fabricated with three N-type drift layer thickness values of 10 μm, 30μm, and 50 μm, respectively. The avalanche breakdown capabilities, static and transient characteristics of the fabricated devices are measured in detail and compared with the theoretical pre- dictions. It is found that the experimental results match well with the theoretical calculation results and are very close to the 4H-SiC theoretical limit line. The best achieved breakdown voltages （BVs） of the diodes on the 10 p.m, 30 m, and 50 -tm epilayers are 1400 V, 3320 V, and 5200 V, respectively. Differential specific-on resistances （Ron-sp） are 2.1 m--cm2, 7.34 mO. cm2, and 30.3 m-. cm2, respectively.

Investigation of a 4H-SiC metal-insulationsemiconductor structure with an A1203/SiO2 stacked dielectric

Atomic layer deposited （ALD） Al2O3/dry-oxidized ultrathin SiO2 films as a high-k gate dielectric grown on 8° off-axis 4H-SiC （0001） epitaxial wafers are investigated in this paper. The metal-insulation-semiconductor （MIS） capacitors, respectively with different gate dielectric stacks （Al2O3/SiO2, Al2O3, and SiO2） are fabricated and compared with each other. The I-V measurements show that the Al2O3/SiO2 stack has a high breakdown field （≥12 MV/cm） comparable to SiO2, and a relatively low gate leakage current of 1 × 10-7 A/cm2 at an electric field of 4 MV/cm comparable to Al2O3. The 1-MHz high frequency C-V measurements exhibit that the Al2O3/SiO2 stack has a smaller positive flat-band voltage shift and hysteresis voltage, indicating a less effective charge and slow-trap density near the interface.

Low specific contact resistance on epitaxial p-type 4H-SiC with a step-bunching surface

This paper reports the performances of Ti/Al based ohmic contacts fabricated on highly doped p-type 4H-SiC epitaxial layer which has a severe step-bunching surface. Different contact schemes are investigated based on the AI：Ti composition with no more than 50 at.% Al. The specific contact resistance （SCR） is obtained to be as low as 2.6 × 10-6Ωcm2 for the bilayered Ti（100 nm）/Al（100 nm） contact treated with 3 rain rapid thermal annealing （RTA） at 1000 ℃. The microstructure analyses examined by physical and chemical characterization techniques reveal an alloy-assisted ohmic contact formation mechanism, i.e., a high degree of alloying plays a decisive role in forming the interfacial ternary Ti3SiC2 dominating the ohmic behavior of the Ti/Al based contact. Furthermore, a globally covered Ti3 SiC2 layer with （0001）-oriented texture can be formed, regardless of the surface step bunching as well as its structural evolution during the metallization annealing.