High-k materials as an alternative dielectric layer for SiC power devices have the potential to reduce interfacial state defects and improve MOS channel conduction capability.Besides,under identical conditions of gate...High-k materials as an alternative dielectric layer for SiC power devices have the potential to reduce interfacial state defects and improve MOS channel conduction capability.Besides,under identical conditions of gate oxide thickness and gate voltage,the high-k dielectric enables a greater charge accumulation in the channel region,resulting in a larger number of free electrons available for conduction.However,the lower energy band gap of high-k materials leads to significant leakage currents at the interface with Si C,which greatly affects device reliability.By inserting a layer of SiO_(2)between the high-k material and Si C,the interfacial barrier can be effectively widened and hence the leakage current will be reduced.In this study,the optimal thickness of the intercalated SiO_(2)was determined by investigating and analyzing the gate dielectric breakdown voltage and interfacial defects of a dielectric stack composed of atomic-layer-deposited Al_(2)O_(3)layer and thermally nitride SiO_(2).Current-voltage and high-frequency capacitance-voltage measurements were performed on metal-oxide-semiconductor test structures with 35 nm thick Al_(2)O_(3)stacked on 1 nm,2 nm,3 nm,6 nm,or 9 nm thick nitride SiO_(2).Measurement results indicated that the current conducted through the oxides was affected by the thickness of the nitride oxide and the applied electric field.Finally,a saturation thickness of stacked SiO_(2)that contributed to dielectric breakdown and interfacial band offsets was identified.The findings in this paper provide a guideline for the SiC gate dielectric stack design with the breakdown strength and the interfacial state defects considered.展开更多
Mesa width （WM） is a key design parameter for SiC super junction （SJ） Schottky diodes （SBD） fabricated by the trench-etching-and-sidewall-implant method. This paper carries out a comprehensive investigation on h...Mesa width （WM） is a key design parameter for SiC super junction （SJ） Schottky diodes （SBD） fabricated by the trench-etching-and-sidewall-implant method. This paper carries out a comprehensive investigation on how the mesa width design determines the device electrical performances and how it affects the degree of performance degradation induced by process variations. It is found that structures designed with narrower mesa widths can tolerant substantially larger charge imbalance for a given BV target, but have poor specific on-resistances. On the contrary, structures with wider mesa widths have superior on-state performances but their breakdown voltages are more sensitive to p-type doping variation. Medium WM structures （-2 p.m） exhibit stronger robustness against the process variation resulting from SiC deep trench etching. Devices with 2-p.m mesa width were fabricated and electrically characterized. The fabricated SiC SJ SBDs have achieved a breakdown voltage of 1350 V with a specific on-resistance as low as 0.98 mΩ2.cm2. The estimated specific drift on- resistance by subtracting substrate resistance is well below the theoretical one-dimensional unipolar limit of SiC material. The robustness of the voltage blocking capability against trench dimension variations has also been experimentally verified for the proposed SiC SJ SBD devices.展开更多
基金Project supported by the Key Area Research and Development Program of Guangdong Province of China(Grant No.2021B0101300005)the National Key Research and Development Program of China(Grant No.2021YFB3401603)。
文摘High-k materials as an alternative dielectric layer for SiC power devices have the potential to reduce interfacial state defects and improve MOS channel conduction capability.Besides,under identical conditions of gate oxide thickness and gate voltage,the high-k dielectric enables a greater charge accumulation in the channel region,resulting in a larger number of free electrons available for conduction.However,the lower energy band gap of high-k materials leads to significant leakage currents at the interface with Si C,which greatly affects device reliability.By inserting a layer of SiO_(2)between the high-k material and Si C,the interfacial barrier can be effectively widened and hence the leakage current will be reduced.In this study,the optimal thickness of the intercalated SiO_(2)was determined by investigating and analyzing the gate dielectric breakdown voltage and interfacial defects of a dielectric stack composed of atomic-layer-deposited Al_(2)O_(3)layer and thermally nitride SiO_(2).Current-voltage and high-frequency capacitance-voltage measurements were performed on metal-oxide-semiconductor test structures with 35 nm thick Al_(2)O_(3)stacked on 1 nm,2 nm,3 nm,6 nm,or 9 nm thick nitride SiO_(2).Measurement results indicated that the current conducted through the oxides was affected by the thickness of the nitride oxide and the applied electric field.Finally,a saturation thickness of stacked SiO_(2)that contributed to dielectric breakdown and interfacial band offsets was identified.The findings in this paper provide a guideline for the SiC gate dielectric stack design with the breakdown strength and the interfacial state defects considered.
基金Project supported by the National Key Research and Development Program of China(Grant No.2016YFB0400502)the National Natural Science Foundation of China(Grant Nos.U1766222 and 51777187)
文摘Mesa width （WM） is a key design parameter for SiC super junction （SJ） Schottky diodes （SBD） fabricated by the trench-etching-and-sidewall-implant method. This paper carries out a comprehensive investigation on how the mesa width design determines the device electrical performances and how it affects the degree of performance degradation induced by process variations. It is found that structures designed with narrower mesa widths can tolerant substantially larger charge imbalance for a given BV target, but have poor specific on-resistances. On the contrary, structures with wider mesa widths have superior on-state performances but their breakdown voltages are more sensitive to p-type doping variation. Medium WM structures （-2 p.m） exhibit stronger robustness against the process variation resulting from SiC deep trench etching. Devices with 2-p.m mesa width were fabricated and electrically characterized. The fabricated SiC SJ SBDs have achieved a breakdown voltage of 1350 V with a specific on-resistance as low as 0.98 mΩ2.cm2. The estimated specific drift on- resistance by subtracting substrate resistance is well below the theoretical one-dimensional unipolar limit of SiC material. The robustness of the voltage blocking capability against trench dimension variations has also been experimentally verified for the proposed SiC SJ SBD devices.
