在当前的CMOS集成电路设计中,利用功率门控技术来降低静态功耗已经成为一种趋势。功率门控技术中,对电路进行分簇的算法和用来生成门控信号的控制电路是主要的设计部分。采用基于门的最大电流进行分簇的BOIG(Based on IMAXof Gate)算法...在当前的CMOS集成电路设计中,利用功率门控技术来降低静态功耗已经成为一种趋势。功率门控技术中,对电路进行分簇的算法和用来生成门控信号的控制电路是主要的设计部分。采用基于门的最大电流进行分簇的BOIG(Based on IMAXof Gate)算法和基于时间的功率门控控制电路,对ISCAS85系列的C432电路和ISCAS89系列的S1238电路进行了功率门控,并在性能、功耗和面积等方面进行了分析。结果表明,在满足性能的要求下,功耗降低了80%以上,面积有所增加。展开更多
This paper presents a novel compact memory in the processing element （PE） for single-instruction multiple-data （SIMD） vision chips. The PE memory is constructed with 8×8 register cells, where one latch in the...This paper presents a novel compact memory in the processing element （PE） for single-instruction multiple-data （SIMD） vision chips. The PE memory is constructed with 8×8 register cells, where one latch in the slave stage is shared by eight latches in the master stage. The memory supports simultaneous read and write on the same address in one clock cycle. Its compact area of 14.33 μm^2/bit promises a higher integration level of the processor. A prototype chip with a 64×64 PE array is fabricated in a UMC 0.18 μm CMOS technology. Five types of the PE memory cell structure are designed and compared. The testing results demonstrate that the proposed PE memory architecture well satisfies the requirement of the vision chip in high-speed real-time vision applications, such as 1000 fps edge extraction.展开更多
This paper presents an image sensor controller that is compatible for depth measurement, which is based on the continuous-wave modulation time-of-flight technology. The image sensor controller is utilized to generate ...This paper presents an image sensor controller that is compatible for depth measurement, which is based on the continuous-wave modulation time-of-flight technology. The image sensor controller is utilized to generate reconfigurable control signals for a 256 × 256 high speed CMOS image sensor with a conventional image sensing mode and a depth measurement mode. The image sensor controller generates control signals for the pixel array to realize the rolling exposure and the correlated double sampling functions. An refined circuit design technique in the logic level is presented to reduce chip area and power consumption. The chip, with a size of 700 × 3380 μm2, is fabricated in a standard 0.18 μm CMOS image sensor process. The power consumption estimated by the synthesis tool is 65 mW under a 1.8 V supply voltage and a 100 MHz clock frequency. Our test results show that the image sensor controller functions properly.展开更多
This paper presents a high-speed column-parallel cyclic analog-to-digital converter（ADC） for a CMOS image sensor.A correlated double sampling（CDS） circuit is integrated in the ADC,which avoids a stand-alone CDS ci...This paper presents a high-speed column-parallel cyclic analog-to-digital converter（ADC） for a CMOS image sensor.A correlated double sampling（CDS） circuit is integrated in the ADC,which avoids a stand-alone CDS circuit block.An offset cancellation technique is also introduced,which reduces the column fixed-pattern noise（FPN） effectively.One single channel ADC with an area less than 0.02 mm^2 was implemented in a 0.13μm CMOS image sensor process.The resolution of the proposed ADC is 10-bit,and the conversion rate is 1.6 MS/s. The measured differential nonlinearity and integral nonlinearity are 0.89 LSB and 6.2 LSB together with CDS, respectively.The power consumption from 3.3 V supply is only 0.66 mW.An array of 48 10-bit column-parallel cyclic ADCs was integrated into an array of CMOS image sensor pixels.The measured results indicated that the ADC circuit is suitable for high-speed CMOS image sensors.展开更多
文摘在当前的CMOS集成电路设计中,利用功率门控技术来降低静态功耗已经成为一种趋势。功率门控技术中,对电路进行分簇的算法和用来生成门控信号的控制电路是主要的设计部分。采用基于门的最大电流进行分簇的BOIG(Based on IMAXof Gate)算法和基于时间的功率门控控制电路,对ISCAS85系列的C432电路和ISCAS89系列的S1238电路进行了功率门控,并在性能、功耗和面积等方面进行了分析。结果表明,在满足性能的要求下,功耗降低了80%以上,面积有所增加。
基金Project supported by the National Natural Science Foundation of China(Nos.60976023,61234003)the Special Funds for Major State Basic Research Project of China(No.2011CB932902)
文摘This paper presents a novel compact memory in the processing element （PE） for single-instruction multiple-data （SIMD） vision chips. The PE memory is constructed with 8×8 register cells, where one latch in the slave stage is shared by eight latches in the master stage. The memory supports simultaneous read and write on the same address in one clock cycle. Its compact area of 14.33 μm^2/bit promises a higher integration level of the processor. A prototype chip with a 64×64 PE array is fabricated in a UMC 0.18 μm CMOS technology. Five types of the PE memory cell structure are designed and compared. The testing results demonstrate that the proposed PE memory architecture well satisfies the requirement of the vision chip in high-speed real-time vision applications, such as 1000 fps edge extraction.
文摘This paper presents an image sensor controller that is compatible for depth measurement, which is based on the continuous-wave modulation time-of-flight technology. The image sensor controller is utilized to generate reconfigurable control signals for a 256 × 256 high speed CMOS image sensor with a conventional image sensing mode and a depth measurement mode. The image sensor controller generates control signals for the pixel array to realize the rolling exposure and the correlated double sampling functions. An refined circuit design technique in the logic level is presented to reduce chip area and power consumption. The chip, with a size of 700 × 3380 μm2, is fabricated in a standard 0.18 μm CMOS image sensor process. The power consumption estimated by the synthesis tool is 65 mW under a 1.8 V supply voltage and a 100 MHz clock frequency. Our test results show that the image sensor controller functions properly.
基金supported by the National Natural Science Foundation of China(Nos.60976023,61234003)the Special Funds for Major State Basic Research Project of China(No.2011CB932902)
文摘This paper presents a high-speed column-parallel cyclic analog-to-digital converter（ADC） for a CMOS image sensor.A correlated double sampling（CDS） circuit is integrated in the ADC,which avoids a stand-alone CDS circuit block.An offset cancellation technique is also introduced,which reduces the column fixed-pattern noise（FPN） effectively.One single channel ADC with an area less than 0.02 mm^2 was implemented in a 0.13μm CMOS image sensor process.The resolution of the proposed ADC is 10-bit,and the conversion rate is 1.6 MS/s. The measured differential nonlinearity and integral nonlinearity are 0.89 LSB and 6.2 LSB together with CDS, respectively.The power consumption from 3.3 V supply is only 0.66 mW.An array of 48 10-bit column-parallel cyclic ADCs was integrated into an array of CMOS image sensor pixels.The measured results indicated that the ADC circuit is suitable for high-speed CMOS image sensors.
