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基于 USB 接口的多通道准高斯型脉冲信号发生器设计 被引量:2
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作者 祁宾祥 刘树彬 +1 位作者 封常青 安琪 《核电子学与探测技术》 CAS CSCD 北大核心 2014年第10期1182-1186,共5页
设计了一种基于USB接口可编程的16通道准高斯型脉冲信号发生器。利用高速模拟开关电路产生模拟脉冲信号,DAC用于调节脉冲信号的幅度,RC网络以及运算放大器组成的成形电路决定脉冲信号的前后沿变时间,通过FPGA来编程控制模拟开关的通断和... 设计了一种基于USB接口可编程的16通道准高斯型脉冲信号发生器。利用高速模拟开关电路产生模拟脉冲信号,DAC用于调节脉冲信号的幅度,RC网络以及运算放大器组成的成形电路决定脉冲信号的前后沿变时间,通过FPGA来编程控制模拟开关的通断和DAC的输出,利用USB接口实现PC机的通信和控制,最终输出16通道的准高斯信号。经测试,实现了预期的功能和要求,输出脉冲幅度大小可调,且各通道输出一致性很好,其积分非线性均小于0.7%,可用于大型粒子物理实验前端电子学的性能测试、校准检测等工作。 展开更多
关键词 多通道 脉冲信号 校准检测
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自由空间量子密钥分发控制系统的FPGA设计 被引量:5
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作者 林泽洪 赵双强 +6 位作者 姜玮 李宠 沈奇 祁宾祥 王潮泽 曹蕾 刘尉悦 《量子电子学报》 CAS CSCD 北大核心 2014年第2期173-178,共6页
在量子保密通信蓬勃发展的今天,基于自由空间的量子密钥分发是一个重要的研究方向。它将在未来全球量子通信网络中扮演重要的角色。介绍了自由空间量子密钥分发控制系统中的电子学设计,选用Xilinx公司的VirtexII-Pro系列芯片,使用内部的... 在量子保密通信蓬勃发展的今天,基于自由空间的量子密钥分发是一个重要的研究方向。它将在未来全球量子通信网络中扮演重要的角色。介绍了自由空间量子密钥分发控制系统中的电子学设计,选用Xilinx公司的VirtexII-Pro系列芯片,使用内部的PowerPC405嵌入式硬核加上功能逻辑模块实现最终量子密钥的提取和外围电路的控制,提高了全系统的集成度和可靠性.该设计成功应用于白天1 km量子密钥分发实验,成码率大于1.5 kbps. 展开更多
关键词 量子信息 量子密钥分发 FPGA 自由空间 嵌入式硬核
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A novel method of encoded multiplexing readout for micro-pattern gas detectors 被引量:1
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作者 祁宾祥 刘树彬 +5 位作者 蓟衡 沈仲弢 马思源 刘宏邦 黄文谦 安琪 《Chinese Physics C》 SCIE CAS CSCD 2016年第5期58-62,共5页
The requirement of a large number of electronic channels poses a big challenge to the further applications of Micro-pattern Gas Detectors (MPGDs). By using the redundancy that at least two neighboring strips record ... The requirement of a large number of electronic channels poses a big challenge to the further applications of Micro-pattern Gas Detectors (MPGDs). By using the redundancy that at least two neighboring strips record the signal of a particle, a novel method of encoded multiplexing readout for MPGDs is presented in this paper. The method offers a feasible and easily-extensible way of encoding and decoding, and can significantly reduce the number of readout channels. A verification test was carried out on a 5 cm×5 cm Thick Gas Electron Multiplier (THGEM) detector using a 8 keV Cu X-ray source with 100um slit, where 166 strips were read out by 21 encoded readout channels. The test results show good linearity in its position response, and the spatial resolution root-mean-square (RMS) of the test system is about 260um. This method has potential to build large area detectors and can be easily adapted to other detectors similar to MPGDs. 展开更多
关键词 micro-pattern gas detector encoded multiplexing readout method position measurement
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A fast improved fat tree encoder for wave union TDC in an FPGA 被引量:3
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作者 沈奇 赵雷 +5 位作者 刘树彬 廖胜凯 祁宾祥 胡雪野 彭承志 安琪 《Chinese Physics C》 SCIE CAS CSCD 2013年第10期56-62,共7页
Up to now, the wave union method can achieve the best timing performance in FPGA-based TDC designs. However, it should be guaranteed in such a structure that the non-thermometer code to binary code (NTH2B) encoding ... Up to now, the wave union method can achieve the best timing performance in FPGA-based TDC designs. However, it should be guaranteed in such a structure that the non-thermometer code to binary code (NTH2B) encoding process should be finished within just one system clock cycle. So the implementation of the NTH2B encoder is quite challenging considering the high speed requirement. Besides, the high resolution wave union TDC also demands that the encoder convert an ultra-wide input code to a binary code. We present a fast improved fat tree encoder (IFTE) to fulfill such requirements, in which bubble error suppression is also integrated. With this encoder scheme, a wave union TDC with 7.7 ps RMS and 3.8 ps effective bin size was implemented in an FPGA from Xilinx Virtex 5 family. An encoding time of 8.33 ns was achieved for a 276-bit non-thermometer code to a 9-bit binary code conversion. We conducted a series of tests on the oscillating period of the wave union launcher, as well as the overall performance of the TDC; test results indicate that the IFTE works well. In fact, in the implementation of this encoder, no manual routing or special constraints were required; therefore, this IFTE structure could also be further applied in other delay-chain-based FPGA TDCs. 展开更多
关键词 wave union TDC FPGA binary encoder time interpolation
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