A low specific on-resistance SOI LDMOS with a novel junction field plate

A low specific on-resistance SO1 LDMOS with a novel junction field plate （JFP） is proposed and investigated theo- retically. The most significant feature of the JFP LDMOS is a PP-N junction field plate instead of a metal field plate. The unique structure not only yields charge compensation between the JFP and the drift region, but also modulates the surface electric field. In addition, a trench gate extends to the buffed oxide layer （BOX） and thus widens the vertical conduction area. As a result, the breakdown voltage （BV） is improved and the specific on-resistance （Ron,sp） is decreased significantly. It is demonstrated that the BV of 306 V and the Ron,sp of 7.43 mΩ.cm2 are obtained for the JFP LDMOS. Compared with those of the conventional LDMOS with the same dimensional parameters, the BV is improved by 34.8%, and the Ron,sp is decreased by 56.6% simultaneously. The proposed JFP LDMOS exhibits significant superiority in terms of the trade-off between BV and Ron,sp. The novel JFP technique offers an alternative technique to achieve high blocking voltage and large current capacity for power devices.

Ultra-low specific on-resistance vertical double-diffused metal-oxide semiconductor with a high-k dielectric-filled extended trench

An ultra-low specific on-resistance trench gate vertical double-diffused metal-oxide semiconductor with a high-k dielectric-filled extended trench（HK TG VDMOS） is proposed in this paper.The HK TG VDMOS features a high-k（HK） trench below the trench gate.Firstly,the extended HK trench not only causes an assistant depletion of the n-drift region,but also optimizes the electric field,which therefore reduces Ron,sp and increases the breakdown voltage（BV）.Secondly,the extended HK trench weakens the sensitivity of BV to the n-drift doping concentration.Thirdly,compared with the superjunction（SJ） vertical double-diffused metal-oxide semiconductor（VDMOS）,the new device is simplified in fabrication by etching and filling the extended trench.The HK TG VDMOS with BV = 172 V and Ron,sp = 0.85 mΩ·cm2 is obtained by simulation;its Ron,sp is reduced by 67% and 40% and its BV is increased by about 15% and 5%,in comparison with those of the conventional trench gate VDMOS（TG VDMOS） and conventional superjunction trench gate VDMOS（SJ TG CDMOS）.

An ultra-low specific on-resistance trench LDMOS with a U-shaped gate and accumulation layer

An ultra-low specific on-resistance （Ron,sp） oxide trench-type silicon-on-insulator （SOI） lateral double-diffusion metal-oxide semiconductor （LDMOS） with an enhanced breakdown voltage （BV） is proposed and investigated by simulation. There are two key features in the proposed device： one is a U-shaped gate around the oxide trench, which extends from source to drain （UG LDMOS）; the other is an N pillar and P pillar located in the trench sidewall. In the on-state, electrons accumulate along the U-shaped gate, providing a continuous low resistance current path from source to drain. The Ron,sp is thus greatly reduced and almost independent of the drift region doping concentration. In the off-state, the N and P pillars not only enhance the electric field （E-field） strength of the trench oxide, but also improve the E-field distribution in the drift region, leading to a significant improvement in the BV. The BV of 662 V and Ron,sp of 12.4 mΩ.cm2 are achieved for the proposed UG LDMOS. The BV is increased by 88.6% and the Ron,sp is reduced by 96.4%, compared with those of the conventional trench LDMOS （CT LDMOS）, realizing the state-of-the-art trade-off between BV and Ron,sp.

A low on-resistance buried current path SOI p-channel LDMOS compatible with n-channel LDMOS

A novel low specific on-resistance （Ron,sp） silicon-on-insulator （SO1） p-channel lateral double-diffused metal-oxide semiconductor （pLDMOS） compatible with high voltage （HV） n-channel LDMOS （nLDMOS） is proposed. The pLDMOS is built in the N-type SO1 layer with a buried P-type layer acting as a current conduction path in the on-state （BP SOl pLD- MOS）. Its superior compatibility with the HV nLDMOS and low voltage （LV） complementary metal-oxide semiconductor （CMOS） circuitry which are formed on the N-SOl layer can be obtained. In the off-state the P-buried layer built in the NSOI layer causes multiple depletion and electric field reshaping, leading to an enhanced （reduced） surface field （RESURF） effect. The proposed BP SO1 pLDMOS achieves not only an improved breakdown voltage （BV） but also a significantly reduced Ron,sp. The BV of the BP SO1 pLDMOS increases to 319 V from 215 V of the conventional SO1 pLDMOS at the same half cell pitch of 25 μm, and Ron,sp decreases from 157 mΩ.cm2 to 55 mΩ.cm2. Compared with the PW SO1 pLDMOS, the BP SO1 pLDMOS also reduces the Ron,sp by 34% with almost the same BV.

A low specific on-resistance SOI MOSFET with dual gates and a recessed drain

A low specific on-resistance（Ron,sp） integrable silicon-on-insulator（SOI） metal-oxide semiconductor field-effect transistor（MOSFET） is proposed and investigated by simulation.The MOSFET features a recessed drain as well as dual gates,which consist of a planar gate and a trench gate extended to the buried oxide layer（BOX）（DGRD MOSFET）.First,the dual gates form dual conduction channels,and the extended trench gate also acts as a field plate to improve the electric field distribution.Second,the combination of the trench gate and the recessed drain widens the vertical conduction area and shortens the current path.Third,the P-type top layer not only enhances the drift doping concentration but also modulates the surface electric field distributions.All of these sharply reduce Ron,sp and maintain a high breakdown voltage（BV）.The BV of 233 V and Ron,sp of 4.151 mΩ·cm2（VGS = 15 V） are obtained for the DGRD MOSFET with 15-μm half-cell pitch.Compared with the trench gate SOI MOSFET and the conventional MOSFET,Ron,sp of the DGRD MOSFET decreases by 36% and 33% with the same BV,respectively.The trench gate extended to the BOX synchronously acts as a dielectric isolation trench,simplifying the fabrication processes.

高k介质电导增强SOI LDMOS机理与优化设计

本文提出一种高k介质电导增强SOI LDMOS新结构(HK CE SOI LDMOS),并研究其机理.HK CE SOI LDMOS的特征是在漂移区两侧引入高k介质,反向阻断时,高k介质对漂移区进行自适应辅助耗尽,实现漂移区三维RESURF效应并调制电场,因而提高器件耐压和漂移区浓度并降低导通电阻.借助三维仿真研究耐压、比导通电阻与器件结构参数之间的关系.结果表明,HK CE SOI LDMOS与常规超结SOI LDMOS相比,耐压提高16%—18%,同时比导通电阻降低13%—20%,且缓解了由衬底辅助耗尽效应带来的电荷非平衡问题.

Experimental and theoretical study of an improved breakdown voltage SOI LDMOS with a reduced cell pitch

An improved breakdown voltage （BV） SOI power MOSFET with a reduced cell pitch is proposed and fabricated. Its breakdown characteristics are investigated numerically and experimentally. The MOSFET features dual trenches （DTMOS）, an oxide trench between the source and drain regions, and a trench gate extended to the buried oxide （BOX）. The proposed device has three merits. First, the oxide trench increases the electric field strength in the x-direction due to the lower permittivity of oxide （eox） than that of Si （esi）. Furthermore, the trench gate, the oxide trench, and the BOX cause multi-directional depletion, improving the electric field distribution and enhancing the RESURF （reduced surface field） effect. Both increase the BV. Second, the oxide trench folds the drift region along the y-direction and thus reduces the cell pitch. Third, the trench gate not only reduces the on-resistance, but also acts as a field plate to improve the BV. Additionally, the trench gate achieves the isolation between high-voltage devices and the low voltage CMOS devices in a high-voltage integrated circuit （HVIC）, effectively saving the chip area and simplifying the isolation process. An 180 V prototype DTMOS with its applied drive IC is fabricated to verify the mechanism.

An L-shaped low on-resistance current path SOI LDMOS with dielectric field enhancement

A low specific on-resistance（R on;sp/ SOI NBL TLDMOS（silicon-on-insulator trench LDMOS with an N buried layer） is proposed. It has three features： a thin N buried layer（NBL） on the interface of the SOI layer/buried oxide（BOX） layer, an oxide trench in the drift region, and a trench gate extended to the BOX layer.First, on the on-state, the electron accumulation layer forms beside the extended trench gate; the accumulation layer and the highly doping NBL constitute an L-shaped low-resistance conduction path, which sharply decreases the R on;sp. Second, in the y-direction, the BOX＇s electric field（E-field） strength is increased to 154 V/ m from48 V/ m of the SOI Trench Gate LDMOS（SOI TG LDMOS） owing to the high doping NBL. Third, the oxide trench increases the lateral E-field strength due to the lower permittivity of oxide than that of Si and strengthens the multiple-directional depletion effect. Fourth, the oxide trench folds the drift region along the y-direction and thus reduces the cell pitch. Therefore, the SOI NBL TLDMOS structure not only increases the breakdown voltage（BV）, but also reduces the cell pitch and R on;sp. Compared with the TG LDMOS, the NBL TLDMOS improves the BV by 105% at the same cell pitch of 6 m, and decreases the R on;sp by 80% at the same BV.

High voltage SOI LDMOS with a compound buried layer

An SOI LDMOS with a compound buried layer（CBL） was proposed.The CBL consists of an upper buried oxide layer（UBOX） with a Si window and two oxide steps,a polysilicon layer and a lower buried oxide layer （LBOX）.In the blocking state,the electric field strengths in the UBOX and LBOX are increased from 88 V/μm of the buried oxide（BOX） in a conventional SOI（C-SOI） LDMOS to 163 V/μm and 460 V/μm by the holes located on the top interfaces of the UBOX and LBOX,respectively.Compared with the C-SOI LDMOS,the CBL LDMOS increases the breakdown voltage from 477 to 847 V,and lowers the maximal temperature by 6 K.