随着射频集成电路空前发展,电感作为射频电路中重要无源器件应用越来越广.目前其仿真模型应用频率范围较窄并且仿真结果与测试结果拟合较差.本文提出了基于0.13μm SOI CMOS工艺的片上螺旋电感修改模型.模型采用了1-π等效电路,包含有...随着射频集成电路空前发展,电感作为射频电路中重要无源器件应用越来越广.目前其仿真模型应用频率范围较窄并且仿真结果与测试结果拟合较差.本文提出了基于0.13μm SOI CMOS工艺的片上螺旋电感修改模型.模型采用了1-π等效电路,包含有表征衬底涡流的RL并联网络并且改进了由趋肤效应引起的金属线圈中涡流的表征.利用数理统计中的回归分析方法,得到扩展模型参数的表达式.制备了13种不同尺寸的片上螺旋电感用于验证模型.本文提出的方法,对不同尺寸的电感在频率达到自谐振频率以上的行为提供了更好的电路解释.展开更多
The hysteresis effect in the output characteristics,originating from the floating body effect,has been measured in partially depleted（PD） silicon-on-insulator（SOI） MOSFETs at different back-gate biases.I D hystere...The hysteresis effect in the output characteristics,originating from the floating body effect,has been measured in partially depleted（PD） silicon-on-insulator（SOI） MOSFETs at different back-gate biases.I D hysteresis has been developed to clarify the hysteresis characteristics.The fabricated devices show the positive and negative peaks in the I D hysteresis.The experimental results show that the I D hysteresis is sensitive to the back gate bias in 0.13-渭m PD SOI MOSFETs and does not vary monotonously with the back-gate bias.Based on the steady-state Shockley-Read-Hall（SRH） recombination theory,we have successfully interpreted the impact of the back-gate bias on the hysteresis effect in PD SOI MOSFETs.展开更多
On the basis of a detailed discussion of the development of total ionizing dose （TID） effect model, a new commercial-model-independent TID modeling approach for partially depleted silicon-on-insulator metal-oxide- s...On the basis of a detailed discussion of the development of total ionizing dose （TID） effect model, a new commercial-model-independent TID modeling approach for partially depleted silicon-on-insulator metal-oxide- semiconductor field effect transistors is developed. An exponential approximation is proposed to simplify the trap charge calculation. Irradiation experiments with 60Co gamma rays for IO and core devices are performed to validate the simulation results. An excellent agreement of measurement with the simulation results is observed.展开更多
Silicon-on-insulator （SOI） technology is attracting a great deal of attention for applications in very large scale integrated circuits due to their excellent proper- ties such as reduced capacitance, higher drive cu...Silicon-on-insulator （SOI） technology is attracting a great deal of attention for applications in very large scale integrated circuits due to their excellent proper- ties such as reduced capacitance, higher drive current and latch-up immunity. The hysteresis effect on the output characteristics could also be important for some special analogous applications reported by Chen et al. The isolation in high density integrated circuits has become very fine to reduce the device size to be- low the sub-0.2 μm regime. For shallow trench isola- tion （STI）, the abrupt transient edge region and the stress between the channel and the isolation region have an undesirable influence on the electrical perfor- mance and reliability. Mechanical stress in the de- vice affects many device characteristics, for example, carrier mobility and hot carrier immunity, and doping diffusion. It is shown for the first time that anoma- lous degradation in time-dependent dielectric break- down （TDDB） for downsized MOSFETs is caused by the compressive stress by STi. An STI-induced en- hanced hot carrier （HC） or negative bias temperature instability （NBTI） effect degradation in p-type MOS- FETs for ultrathin gate oxide devices has been ob- served in Ref. The behavior of the STI disloca- tions and the effect on the junction leakage character- istics during the fabrication of dynamic random access memory （DRAM） with 0.15m technology have been reported in Ref. . In this work, we investigate the influence of STI mechanical stress on the hysteresis effect of PD SOI NMOS devices.展开更多
A gate-to-body tunneling current model for silicon-on-insulator （SOl） devices is simulated. As verified by the mea- sured data, the model, considering both gate voltage and drain voltage dependence as well as image ...A gate-to-body tunneling current model for silicon-on-insulator （SOl） devices is simulated. As verified by the mea- sured data, the model, considering both gate voltage and drain voltage dependence as well as image force-induced barrier low effect, provides a better prediction of the tunneling current and gate-induced floating body effect than the BSIMSOI4 model. A delayed gate-induced floating body effect is also predicted by the model.展开更多
The asymmetric underlap device for a floating body cell is proposed without any extra process or photomask during fabrication.The electric field in the gate-drain underlap region is quietly relaxed.It is found that me...The asymmetric underlap device for a floating body cell is proposed without any extra process or photomask during fabrication.The electric field in the gate-drain underlap region is quietly relaxed.It is found that memory operation would fail in bipolar-based floating body cells because band-to-band tunneling significantly alters the body potential.Measurements show the proposed structure could indeed suppress the undesirable band-to-band tunneling greatly so that the bistable state via the parasitic bipolar junction transistor is ensured in scaled floating body cells.The parasitic capacitances in both word line and bit line are also reduced.展开更多
The effects of back gate bias(BGEs) on radio-frequency(RF) performances in PD SOI n MOSFETs are presented in this paper. Floating body(FB) device, T-gate body-contact(TB) device, and tunnel diode body-contact(TDBC) de...The effects of back gate bias(BGEs) on radio-frequency(RF) performances in PD SOI n MOSFETs are presented in this paper. Floating body(FB) device, T-gate body-contact(TB) device, and tunnel diode body-contact(TDBC) device, of which the supply voltages are all 1.2 V, are compared under different back gate biases by different figures of merit, such as cut-off frequency( fT), maximum frequency of oscillation( fmax), etc. Because of the lack of a back gate conducting channel, the drain conductance(gd) of TDBC transistor shows a smaller degradation than those of the others, and the trans-conductance(gm) of TDBC is almost independent of back gate bias. The values of fT of TDBC are also kept nearly constant under different back gate biases. However, RF performances of FB and TB each show a significant degradation when the back gate bias is larger than ～ 20 V. The results indicate that TDBC structures could effectively improve the back gate bias in RF performance.展开更多
Radio-frequency（RF） characteristics under ultra-low temperature of multi-finger partially depleted silicon-oninsulator（PD SOI） n-type metal-oxide-semiconductor field-effect transistors（nMOSFETs） with tunnel diod...Radio-frequency（RF） characteristics under ultra-low temperature of multi-finger partially depleted silicon-oninsulator（PD SOI） n-type metal-oxide-semiconductor field-effect transistors（nMOSFETs） with tunnel diode body-contact（TDBC） structure and T-gate body-contact（TB） structure are investigated in this paper.When operating at 77 K,TDBC device suppresses floating-body effect（FBE） as well as the TB device.For TB device and TDBC device,cut-off frequency（fT） improves as the temperature decreases to liquid-helium temperature（77 K） while that of the maximum oscillation frequency（/max） is opposite due to the decrease of the unilateral power gain.While operating under 77 K,fT and f（max） of TDBC device reach to 125 GHz and 77 GHz,representing 8%and 15% improvements compared with those of TB device,respectively,which is mainly due to the lower parasitic resistances and capacitances.The results indicate that TDBC SOI MOSFETs could be considered as promising candidates for analog and RF applications over a wide range of temperatures and there is immense potential for the development of RF CMOS integrated circuits for cryogenic applications.展开更多
文摘随着射频集成电路空前发展,电感作为射频电路中重要无源器件应用越来越广.目前其仿真模型应用频率范围较窄并且仿真结果与测试结果拟合较差.本文提出了基于0.13μm SOI CMOS工艺的片上螺旋电感修改模型.模型采用了1-π等效电路,包含有表征衬底涡流的RL并联网络并且改进了由趋肤效应引起的金属线圈中涡流的表征.利用数理统计中的回归分析方法,得到扩展模型参数的表达式.制备了13种不同尺寸的片上螺旋电感用于验证模型.本文提出的方法,对不同尺寸的电感在频率达到自谐振频率以上的行为提供了更好的电路解释.
基金Project supported by the TCAD Simulation and SPICE Modeling of 0.13μm SOI Technology,China (Grant No. 2009ZX02306-002)
文摘The hysteresis effect in the output characteristics,originating from the floating body effect,has been measured in partially depleted（PD） silicon-on-insulator（SOI） MOSFETs at different back-gate biases.I D hysteresis has been developed to clarify the hysteresis characteristics.The fabricated devices show the positive and negative peaks in the I D hysteresis.The experimental results show that the I D hysteresis is sensitive to the back gate bias in 0.13-渭m PD SOI MOSFETs and does not vary monotonously with the back-gate bias.Based on the steady-state Shockley-Read-Hall（SRH） recombination theory,we have successfully interpreted the impact of the back-gate bias on the hysteresis effect in PD SOI MOSFETs.
基金Supported by the National Natural Science Foundation of China under Grant Nos 61404151 and 61574153
文摘On the basis of a detailed discussion of the development of total ionizing dose （TID） effect model, a new commercial-model-independent TID modeling approach for partially depleted silicon-on-insulator metal-oxide- semiconductor field effect transistors is developed. An exponential approximation is proposed to simplify the trap charge calculation. Irradiation experiments with 60Co gamma rays for IO and core devices are performed to validate the simulation results. An excellent agreement of measurement with the simulation results is observed.
文摘Silicon-on-insulator （SOI） technology is attracting a great deal of attention for applications in very large scale integrated circuits due to their excellent proper- ties such as reduced capacitance, higher drive current and latch-up immunity. The hysteresis effect on the output characteristics could also be important for some special analogous applications reported by Chen et al. The isolation in high density integrated circuits has become very fine to reduce the device size to be- low the sub-0.2 μm regime. For shallow trench isola- tion （STI）, the abrupt transient edge region and the stress between the channel and the isolation region have an undesirable influence on the electrical perfor- mance and reliability. Mechanical stress in the de- vice affects many device characteristics, for example, carrier mobility and hot carrier immunity, and doping diffusion. It is shown for the first time that anoma- lous degradation in time-dependent dielectric break- down （TDDB） for downsized MOSFETs is caused by the compressive stress by STi. An STI-induced en- hanced hot carrier （HC） or negative bias temperature instability （NBTI） effect degradation in p-type MOS- FETs for ultrathin gate oxide devices has been ob- served in Ref. The behavior of the STI disloca- tions and the effect on the junction leakage character- istics during the fabrication of dynamic random access memory （DRAM） with 0.15m technology have been reported in Ref. . In this work, we investigate the influence of STI mechanical stress on the hysteresis effect of PD SOI NMOS devices.
文摘A gate-to-body tunneling current model for silicon-on-insulator （SOl） devices is simulated. As verified by the mea- sured data, the model, considering both gate voltage and drain voltage dependence as well as image force-induced barrier low effect, provides a better prediction of the tunneling current and gate-induced floating body effect than the BSIMSOI4 model. A delayed gate-induced floating body effect is also predicted by the model.
文摘The asymmetric underlap device for a floating body cell is proposed without any extra process or photomask during fabrication.The electric field in the gate-drain underlap region is quietly relaxed.It is found that memory operation would fail in bipolar-based floating body cells because band-to-band tunneling significantly alters the body potential.Measurements show the proposed structure could indeed suppress the undesirable band-to-band tunneling greatly so that the bistable state via the parasitic bipolar junction transistor is ensured in scaled floating body cells.The parasitic capacitances in both word line and bit line are also reduced.
文摘The effects of back gate bias(BGEs) on radio-frequency(RF) performances in PD SOI n MOSFETs are presented in this paper. Floating body(FB) device, T-gate body-contact(TB) device, and tunnel diode body-contact(TDBC) device, of which the supply voltages are all 1.2 V, are compared under different back gate biases by different figures of merit, such as cut-off frequency( fT), maximum frequency of oscillation( fmax), etc. Because of the lack of a back gate conducting channel, the drain conductance(gd) of TDBC transistor shows a smaller degradation than those of the others, and the trans-conductance(gm) of TDBC is almost independent of back gate bias. The values of fT of TDBC are also kept nearly constant under different back gate biases. However, RF performances of FB and TB each show a significant degradation when the back gate bias is larger than ～ 20 V. The results indicate that TDBC structures could effectively improve the back gate bias in RF performance.
文摘Radio-frequency（RF） characteristics under ultra-low temperature of multi-finger partially depleted silicon-oninsulator（PD SOI） n-type metal-oxide-semiconductor field-effect transistors（nMOSFETs） with tunnel diode body-contact（TDBC） structure and T-gate body-contact（TB） structure are investigated in this paper.When operating at 77 K,TDBC device suppresses floating-body effect（FBE） as well as the TB device.For TB device and TDBC device,cut-off frequency（fT） improves as the temperature decreases to liquid-helium temperature（77 K） while that of the maximum oscillation frequency（/max） is opposite due to the decrease of the unilateral power gain.While operating under 77 K,fT and f（max） of TDBC device reach to 125 GHz and 77 GHz,representing 8%and 15% improvements compared with those of TB device,respectively,which is mainly due to the lower parasitic resistances and capacitances.The results indicate that TDBC SOI MOSFETs could be considered as promising candidates for analog and RF applications over a wide range of temperatures and there is immense potential for the development of RF CMOS integrated circuits for cryogenic applications.
