在多用户认知无线电OFDM系统中,针对实时视频业务用户,提出一种计算复杂度低的资源分配方案。该方案采用鱼群算法分配子载波,并提出简单功率干扰(Simple Power Interference,SPI)约束功率分配算法。目标是在满足总功率预算并且保证不干...在多用户认知无线电OFDM系统中,针对实时视频业务用户,提出一种计算复杂度低的资源分配方案。该方案采用鱼群算法分配子载波,并提出简单功率干扰(Simple Power Interference,SPI)约束功率分配算法。目标是在满足总功率预算并且保证不干扰主用户的前提下,最大化系统的下行系统容量。仿真分析表明,在视频业务用户场景中,所提算法能有效提高下行系统速率,性能接近最优且复杂度低。展开更多
This paper proposes a novel noise optimization technique.The technique gives analytical formulae for the noise performance of inductively degenerated CMOS low noise amplifier（LNA）circuits with an ideal gate inductor...This paper proposes a novel noise optimization technique.The technique gives analytical formulae for the noise performance of inductively degenerated CMOS low noise amplifier（LNA）circuits with an ideal gate inductor for a fixed bias voltage and nonideal gate inductor for a fixed power dissipation,respectively,by mathematical analysis and reasonable approximation methods.LNA circuits with required noise figure can be designed effectively and rapidly just by using hand calculations of the proposed formulae.We design a 1.8 GHz LNA in a TSMC 0.25 μm CMOS process.The measured results show a noise figure of 1.6 dB with a forward gain of 14.4 dB at a power consumption of 5 mW,demonstrating that the designed LNA circuits can achieve low noise figure levels at low power dissipation.展开更多
This work presents the design and implementation of a 2.4 GHz low power fast-settling frequency-presetting PLL frequency synthesizer in the 0.18μm CMOS process.A low power mixed-signal LC VCO,a low power dual mode pr...This work presents the design and implementation of a 2.4 GHz low power fast-settling frequency-presetting PLL frequency synthesizer in the 0.18μm CMOS process.A low power mixed-signal LC VCO,a low power dual mode prescaler and a digital processor with non-volatile memory are developed to greatly reduce the power consumption and the setting time.The digital processor can automatically calibrate the presetting frequency and accurately preset the frequency of the VCO under process variations.The experimental results demonstrate that the power consumption of the synthesizer is about 4 mA @ 1.8 V and that the typical setting time of the synthesizer is less than 3μs.展开更多
This paper presents the design and implementation of a low power wide tuning range baseband filter with an accurate on-chip tuning circuit for reconfigurable multistandard wireless transceivers. The realized low pass ...This paper presents the design and implementation of a low power wide tuning range baseband filter with an accurate on-chip tuning circuit for reconfigurable multistandard wireless transceivers. The realized low pass filter （LPF） is a six-order Butterworth type by cascading three stage active-Gm-RC biquadratic cells. A mod- ified linearization technique is used to improve the filter linearity performance at low power consumption. A new process-independent transconductor matching circuit and a new frequency tuning circuit with frequency compen- sation are proposed to achieve a high precision filter frequency response. The proposed LPF is realized in a 130 nm standard CMOS technology. The measured results show that the LPF exhibits a high bandwidth programmability from 0.1 to 25 MHz with a tuning frequency error less than 2.68% over the wide tuning range. The power consump- tion is scalable, ranging from 0.52 to 5.25 mA, from a 1.2 V power supply while achieving a 26.3 dBm in-band IIP3.展开更多
This paper proposes a sigma-delta fractional-N frequency synthesizer-based multi-standard I/Q carrier generation system.With reasonable frequency planning,the system can be used in multi-standard wireless communicatio...This paper proposes a sigma-delta fractional-N frequency synthesizer-based multi-standard I/Q carrier generation system.With reasonable frequency planning,the system can be used in multi-standard wireless communication applications（GSM,WCDMA,GPRS,TD-SCDMA,WLAN（802.11a/b/g））.The implementation is achieved by a 0.13μm RF CMOS process.The measured results demonstrate that three quadrature VCOs（QVCO） continuously cover the frequency from 3.1 to 6.1 GHz（65.2%）,and through the successive divide-by-2 prescalers to achieve the frequency from 0.75 to 6.1 GHz continuously.The chip was fully integrated with the exception of an off-chip filter.The entire chip area is only 3.78 mm^2,and the system consumes a 21.7 mA@1.2 V supply without output buffers.The lock-in time of the PLL frequency synthesizer is less than 4μs over the entire frequency range with a direct frequency presetting technique and the auxiliary non-volatile memory（NVM）can store the digital configuration signal of the system,including presetting signals to avoid the calibration process case by case.展开更多
This paper proposes a new structure to lower the power consumption of a variable gain amplifier（VGA） and keep the linearity of the VGA unchanged.The structure is used in a high rate amplitude-shift keying（ASK） bas...This paper proposes a new structure to lower the power consumption of a variable gain amplifier（VGA） and keep the linearity of the VGA unchanged.The structure is used in a high rate amplitude-shift keying（ASK） based IF-stage.It includes an automatic gain control（AGC） loop and ASK demodulator.The AGC mainly consists of sixstage VGAs.The IF-stage is realized in 0.18μm CMOS technology.The measurement results show that the power consumption of the whole system is very low.The system consumes 730μA while operating at 1.8 V.The minimum ASK signal the system could detect is 0.7 mV（peak to peak amplitude）.展开更多
文摘在多用户认知无线电OFDM系统中,针对实时视频业务用户,提出一种计算复杂度低的资源分配方案。该方案采用鱼群算法分配子载波,并提出简单功率干扰(Simple Power Interference,SPI)约束功率分配算法。目标是在满足总功率预算并且保证不干扰主用户的前提下,最大化系统的下行系统容量。仿真分析表明,在视频业务用户场景中,所提算法能有效提高下行系统速率,性能接近最优且复杂度低。
文摘计算机视觉智能设备可以帮助人们进行垃圾分类,提高垃圾分类回收效率。为了降低平台体积功耗存储及计算能力的要求,更利于模型部署在资源有限的移动端,本文基于YOLOv4目标检测算法,提出一种改进的轻量化网络。采用轻量级的Ghost Net特征提取网络作为主干网络,使用Ghost Module结构代替普通卷积,并引入坐标注意力机制。模型体积所占内存压缩到40.5MB,在自制垃圾检测数据集上达到了94.28%的全类平均精度(mean Average Precision,mAP),并将系统成功部署在安卓手机端。该系统实现了模型压缩,加快了检测速度,使得算法能够部署在资源有限的边缘设备。
基金supported by the National Natural Science Foundation of China(No.90607007)the State Key Development Program for Basic Research of China(Nos.2006AA04A108,2008AA010703)
文摘This paper proposes a novel noise optimization technique.The technique gives analytical formulae for the noise performance of inductively degenerated CMOS low noise amplifier（LNA）circuits with an ideal gate inductor for a fixed bias voltage and nonideal gate inductor for a fixed power dissipation,respectively,by mathematical analysis and reasonable approximation methods.LNA circuits with required noise figure can be designed effectively and rapidly just by using hand calculations of the proposed formulae.We design a 1.8 GHz LNA in a TSMC 0.25 μm CMOS process.The measured results show a noise figure of 1.6 dB with a forward gain of 14.4 dB at a power consumption of 5 mW,demonstrating that the designed LNA circuits can achieve low noise figure levels at low power dissipation.
基金Project supported by the National High-Tech Research and Development Program of China(Nos.2008AA010703,2009AA011606).
文摘This work presents the design and implementation of a 2.4 GHz low power fast-settling frequency-presetting PLL frequency synthesizer in the 0.18μm CMOS process.A low power mixed-signal LC VCO,a low power dual mode prescaler and a digital processor with non-volatile memory are developed to greatly reduce the power consumption and the setting time.The digital processor can automatically calibrate the presetting frequency and accurately preset the frequency of the VCO under process variations.The experimental results demonstrate that the power consumption of the synthesizer is about 4 mA @ 1.8 V and that the typical setting time of the synthesizer is less than 3μs.
基金supported by the Scientific Research Plan Projects of Hebei Education Department(No.Q2012019)
文摘This paper presents the design and implementation of a low power wide tuning range baseband filter with an accurate on-chip tuning circuit for reconfigurable multistandard wireless transceivers. The realized low pass filter （LPF） is a six-order Butterworth type by cascading three stage active-Gm-RC biquadratic cells. A mod- ified linearization technique is used to improve the filter linearity performance at low power consumption. A new process-independent transconductor matching circuit and a new frequency tuning circuit with frequency compen- sation are proposed to achieve a high precision filter frequency response. The proposed LPF is realized in a 130 nm standard CMOS technology. The measured results show that the LPF exhibits a high bandwidth programmability from 0.1 to 25 MHz with a tuning frequency error less than 2.68% over the wide tuning range. The power consump- tion is scalable, ranging from 0.52 to 5.25 mA, from a 1.2 V power supply while achieving a 26.3 dBm in-band IIP3.
基金Project supported by the Chinese National High-Tech Research and Development Program(Nos2009ZX03007-001,2009AA011606)the National Natural Science Foundation of China(No60976023)
文摘This paper proposes a sigma-delta fractional-N frequency synthesizer-based multi-standard I/Q carrier generation system.With reasonable frequency planning,the system can be used in multi-standard wireless communication applications（GSM,WCDMA,GPRS,TD-SCDMA,WLAN（802.11a/b/g））.The implementation is achieved by a 0.13μm RF CMOS process.The measured results demonstrate that three quadrature VCOs（QVCO） continuously cover the frequency from 3.1 to 6.1 GHz（65.2%）,and through the successive divide-by-2 prescalers to achieve the frequency from 0.75 to 6.1 GHz continuously.The chip was fully integrated with the exception of an off-chip filter.The entire chip area is only 3.78 mm^2,and the system consumes a 21.7 mA@1.2 V supply without output buffers.The lock-in time of the PLL frequency synthesizer is less than 4μs over the entire frequency range with a direct frequency presetting technique and the auxiliary non-volatile memory（NVM）can store the digital configuration signal of the system,including presetting signals to avoid the calibration process case by case.
基金supported by the National High-Tech Research and Development Program of China(Nos.2008AA010703,2009AA011606)the National Natural Science Foundation of China(No.60976023)
文摘This paper proposes a new structure to lower the power consumption of a variable gain amplifier（VGA） and keep the linearity of the VGA unchanged.The structure is used in a high rate amplitude-shift keying（ASK） based IF-stage.It includes an automatic gain control（AGC） loop and ASK demodulator.The AGC mainly consists of sixstage VGAs.The IF-stage is realized in 0.18μm CMOS technology.The measurement results show that the power consumption of the whole system is very low.The system consumes 730μA while operating at 1.8 V.The minimum ASK signal the system could detect is 0.7 mV（peak to peak amplitude）.
