Nanowires with gate-all-around(GAA) structures are widely considered as the most promising candidate for 3-nm technology with the best ability of suppressing the short channel effects,and tunneling field effect transi...Nanowires with gate-all-around(GAA) structures are widely considered as the most promising candidate for 3-nm technology with the best ability of suppressing the short channel effects,and tunneling field effect transistors(TFETs)based on GAA structures also present improved performance.In this paper,a non-quasi-static(NQS) device model is developed for nanowire GAA TFETs.The model can predict the transient current and capacitance varying with operation frequency,which is beyond the ability of the quasi-static(QS) model published before.Excellent agreements between the model results and numerical simulations are obtained.Moreover,the NQS model is derived from the published QS model including the current-voltage(I-V) and capacitance-voltage(C-V) characteristics.Therefore,the NQS model is compatible with the QS model for giving comprehensive understanding of GAA TFETs and would be helpful for further study of TFET circuits based on nanowire GAA structure.展开更多
To solve the problem of the low on-state current in p-type tunnel field-effect transistors(p-TFETs),this paper analyzes the mechanism of adjusting the tunneling current of a TFET device determined by studying the infl...To solve the problem of the low on-state current in p-type tunnel field-effect transistors(p-TFETs),this paper analyzes the mechanism of adjusting the tunneling current of a TFET device determined by studying the influence of the peak position of ion implantation on the potential of the p-TFET device surface and the width of the tunneling barrier.Doping-regulated silicon-based high on-state p-TFET devices are designed and fabricated,and the test results show that the on-state current of the fabricated devices can be increased by about two orders of magnitude compared with the current of other devices with the same structure.This method provides a new idea for the realization of high on-state current TFET devices.展开更多
Due to the pristine interface of the 2D/3D face-tunneling heterostructure with an ultra-sharp doping profile, the 2D/3D tunneling field-effect transistor(TFET) is considered as one of the most promising low-power devi...Due to the pristine interface of the 2D/3D face-tunneling heterostructure with an ultra-sharp doping profile, the 2D/3D tunneling field-effect transistor(TFET) is considered as one of the most promising low-power devices that can simultaneously obtain low off-state current(IOFF), high on-state current(ION) and steep subthreshold swing(SS). As a key element for the 2D/3D TFET, the intensive exploration of the tunnel diode based on the 2D/3D heterostructure is in urgent need.The transfer technique composed of the exfoliation and the release process is currently the most common approach to fabricating the 2D/3D heterostructures. However, the well-established transfer technique of the 2D materials is still unavailable.Only a small part of the irregular films can usually be obtained by mechanical exfoliation, while the choice of the chemical exfoliation may lead to the contamination of the 2D material films by the ions in the chemical etchants. Moreover, the deformation of the 2D material in the transfer process due to its soft nature also leads to the nonuniformity of the transferred film,which is one of the main reasons for the presence of the wrinkles and the stacks in the transferred film. Thus, the large-scale fabrication of the high-quality 2D/3D tunnel diodes is limited. In this article, a comprehensive transfer technique that can mend up the shortages mentioned above with the aid of the water and the thermal release tape(TRT) is proposed. Based on the method we proposed, the MoS_(2)/Si tunnel diode is experimentally demonstrated and the transferred monolayer MoS_(2) film with the relatively high crystal quality is confirmed by atomic force microscopy(AFM), scanning electron microscopy(SEM), and Raman characterizations. Besides, the prominent negative differential resistance(NDR) effect is observed at room temperature, which verifies the relatively high quality of the MoS_(2)/Si heterojunction. The bilayer MoS_(2)/Si tunnel diode is also experimentally fabricated by repeating the transfer process we proposed, followed by the specific analysis of the electrical characteristics. This study shows the advantages of the transfer technique we proposed and indicates the great application foreground of the fabricated 2D/3D heterostructure for ultralow-power tunneling devices.展开更多
In this paper, an efficient thermal analysis method is presented for large scale compound semiconductor integrated circuits based on a heterojunction bipolar transistor with considering the change of thermal conductiv...In this paper, an efficient thermal analysis method is presented for large scale compound semiconductor integrated circuits based on a heterojunction bipolar transistor with considering the change of thermal conductivity with temperature.The influence caused by the thermal conductivity can be equivalent to the increment of the local temperature surrounding the individual device. The junction temperature for each device can be efficiently calculated by the combination of the semianalytic temperature distribution function and the iteration of local temperature with high accuracy, providing a temperature distribution for a full chip. Applying this method to the InP frequency divider chip and the GaAs analog to digital converter chip, the computational results well agree with the results from the simulator COMSOL and the infrared thermal imager respectively. The proposed method can also be applied to thermal analysis in various kinds of semiconductor integrated circuits.展开更多
A novel vertical graded source tunnel field-effect transistor(VGS-TFET)is proposed to improve device performance.By introducing a source with linearly graded component,the on-state current increases by more than two d...A novel vertical graded source tunnel field-effect transistor(VGS-TFET)is proposed to improve device performance.By introducing a source with linearly graded component,the on-state current increases by more than two decades higher than that of the conventional GaAs TFETs without sacrificing the subthreshold swing(SS)due to the improved band-to-band tunneling efficiency.Compared with the conventional TFETs,much larger drive current range can be achieved by the proposed VGS-TFET with SS below the thermionic limitation of 60 mV/dec.Furthermore,the minimum SS about 20 mV/dec indicates its promising potential for further ultralow power applications.展开更多
We have investigated the temperature dependent interfacial and electrical characteristics of p-Ga As metal–oxide–semiconductor capacitors during atomic layer deposition(ALD) and annealing of HfO_2 using the tetrakis...We have investigated the temperature dependent interfacial and electrical characteristics of p-Ga As metal–oxide–semiconductor capacitors during atomic layer deposition(ALD) and annealing of HfO_2 using the tetrakis(ethylmethyl) amino hafnium precursor. The leakage current decreases with the increase of the ALD temperature and the lowest current is obtained at 300 ℃ as a result of the Frenkel-Poole conduction induced leakage current being greatly weakened by the reduction of interfacial oxides at the higher temperature. Post deposition annealing(PDA) at 500 ℃ after ALD at 300 ℃ leads to the lowest leakage current compared with other annealing temperatures. A pronounced reduction in As oxides during PDA at 500 ℃ has been observed using X-ray photoelectron spectroscopy at the interface resulting in a proportional increase in Ga_2O_3. The increment of Ga_2O_3 after PDA depends on the amount of residual As oxides after ALD. Thus, the ALD temperature plays an important role in determining the high-k/Ga As interface condition. Meanwhile, an optimum PDA temperature is essential for obtaining good dielectric properties.展开更多
基金Project supported by the National Natural Science Foundation of China (Grant Nos. 62004119 and 62201332)the Applied Basic Research Plan of Shanxi Province, China (Grant Nos. 20210302124647 and 20210302124028)。
文摘Nanowires with gate-all-around(GAA) structures are widely considered as the most promising candidate for 3-nm technology with the best ability of suppressing the short channel effects,and tunneling field effect transistors(TFETs)based on GAA structures also present improved performance.In this paper,a non-quasi-static(NQS) device model is developed for nanowire GAA TFETs.The model can predict the transient current and capacitance varying with operation frequency,which is beyond the ability of the quasi-static(QS) model published before.Excellent agreements between the model results and numerical simulations are obtained.Moreover,the NQS model is derived from the published QS model including the current-voltage(I-V) and capacitance-voltage(C-V) characteristics.Therefore,the NQS model is compatible with the QS model for giving comprehensive understanding of GAA TFETs and would be helpful for further study of TFET circuits based on nanowire GAA structure.
基金Project supported by the Key Research and Development Program of Shaanxi(Grant No.2021GY-010)the National Defense Science and Technology Foundation Strengthening Program of China(Grant No.2019-XXXX-XX-236-00).
文摘To solve the problem of the low on-state current in p-type tunnel field-effect transistors(p-TFETs),this paper analyzes the mechanism of adjusting the tunneling current of a TFET device determined by studying the influence of the peak position of ion implantation on the potential of the p-TFET device surface and the width of the tunneling barrier.Doping-regulated silicon-based high on-state p-TFET devices are designed and fabricated,and the test results show that the on-state current of the fabricated devices can be increased by about two orders of magnitude compared with the current of other devices with the same structure.This method provides a new idea for the realization of high on-state current TFET devices.
基金Project supported by the National Natural Science Foundation of China (Grant No.61851405)。
文摘Due to the pristine interface of the 2D/3D face-tunneling heterostructure with an ultra-sharp doping profile, the 2D/3D tunneling field-effect transistor(TFET) is considered as one of the most promising low-power devices that can simultaneously obtain low off-state current(IOFF), high on-state current(ION) and steep subthreshold swing(SS). As a key element for the 2D/3D TFET, the intensive exploration of the tunnel diode based on the 2D/3D heterostructure is in urgent need.The transfer technique composed of the exfoliation and the release process is currently the most common approach to fabricating the 2D/3D heterostructures. However, the well-established transfer technique of the 2D materials is still unavailable.Only a small part of the irregular films can usually be obtained by mechanical exfoliation, while the choice of the chemical exfoliation may lead to the contamination of the 2D material films by the ions in the chemical etchants. Moreover, the deformation of the 2D material in the transfer process due to its soft nature also leads to the nonuniformity of the transferred film,which is one of the main reasons for the presence of the wrinkles and the stacks in the transferred film. Thus, the large-scale fabrication of the high-quality 2D/3D tunnel diodes is limited. In this article, a comprehensive transfer technique that can mend up the shortages mentioned above with the aid of the water and the thermal release tape(TRT) is proposed. Based on the method we proposed, the MoS_(2)/Si tunnel diode is experimentally demonstrated and the transferred monolayer MoS_(2) film with the relatively high crystal quality is confirmed by atomic force microscopy(AFM), scanning electron microscopy(SEM), and Raman characterizations. Besides, the prominent negative differential resistance(NDR) effect is observed at room temperature, which verifies the relatively high quality of the MoS_(2)/Si heterojunction. The bilayer MoS_(2)/Si tunnel diode is also experimentally fabricated by repeating the transfer process we proposed, followed by the specific analysis of the electrical characteristics. This study shows the advantages of the transfer technique we proposed and indicates the great application foreground of the fabricated 2D/3D heterostructure for ultralow-power tunneling devices.
基金Project supported by the Advance Research Foundation of China(Grant No.9140Axxx501)the National Defense Advance Research Project,China(Grant No.3151xxxx301)+1 种基金the Frontier Innovation Program,China(Grant No.48xx4)the 111 Project,China(Grant No.B12026)
文摘In this paper, an efficient thermal analysis method is presented for large scale compound semiconductor integrated circuits based on a heterojunction bipolar transistor with considering the change of thermal conductivity with temperature.The influence caused by the thermal conductivity can be equivalent to the increment of the local temperature surrounding the individual device. The junction temperature for each device can be efficiently calculated by the combination of the semianalytic temperature distribution function and the iteration of local temperature with high accuracy, providing a temperature distribution for a full chip. Applying this method to the InP frequency divider chip and the GaAs analog to digital converter chip, the computational results well agree with the results from the simulator COMSOL and the infrared thermal imager respectively. The proposed method can also be applied to thermal analysis in various kinds of semiconductor integrated circuits.
基金Project supported by the National Natural Science Foundation of China(Grant No.90304190002).
文摘A novel vertical graded source tunnel field-effect transistor(VGS-TFET)is proposed to improve device performance.By introducing a source with linearly graded component,the on-state current increases by more than two decades higher than that of the conventional GaAs TFETs without sacrificing the subthreshold swing(SS)due to the improved band-to-band tunneling efficiency.Compared with the conventional TFETs,much larger drive current range can be achieved by the proposed VGS-TFET with SS below the thermionic limitation of 60 mV/dec.Furthermore,the minimum SS about 20 mV/dec indicates its promising potential for further ultralow power applications.
基金supported by the Advance Research Project of China(No.5130803XXXX)the National Natural Science Foundation of China(No.61176070)
文摘We have investigated the temperature dependent interfacial and electrical characteristics of p-Ga As metal–oxide–semiconductor capacitors during atomic layer deposition(ALD) and annealing of HfO_2 using the tetrakis(ethylmethyl) amino hafnium precursor. The leakage current decreases with the increase of the ALD temperature and the lowest current is obtained at 300 ℃ as a result of the Frenkel-Poole conduction induced leakage current being greatly weakened by the reduction of interfacial oxides at the higher temperature. Post deposition annealing(PDA) at 500 ℃ after ALD at 300 ℃ leads to the lowest leakage current compared with other annealing temperatures. A pronounced reduction in As oxides during PDA at 500 ℃ has been observed using X-ray photoelectron spectroscopy at the interface resulting in a proportional increase in Ga_2O_3. The increment of Ga_2O_3 after PDA depends on the amount of residual As oxides after ALD. Thus, the ALD temperature plays an important role in determining the high-k/Ga As interface condition. Meanwhile, an optimum PDA temperature is essential for obtaining good dielectric properties.
