A12-Bit 40-MS/s pipelined analog-to-digital converter （ADC） incorporates a front-end RC constant matching technique and a set of front-end timing with different duty cycle that are beneficial for enhancing linearity...A12-Bit 40-MS/s pipelined analog-to-digital converter （ADC） incorporates a front-end RC constant matching technique and a set of front-end timing with different duty cycle that are beneficial for enhancing linearity in SHA-less architecture without tedious verification in back-end layout simulation. Employing SHA-less, opampsharing and low-power opamps for low dissipation and low cost, designed in 0.13μm CMOS technology, the prototype digitizes a 10.2-MHz input with 78.2-dB of spurious free dynamic range, 60.5-dB of signal-to-noise- and-distortion ratio, and -75.5-dB of total harmonic distortion （the first 5 harmonics included） while consuming 15.6-mW from a 1.2-V supply.展开更多
A novel low-voltage two-stage operational amplifier employing class-AB architecture is presented. The structure utilizes level-shifters and current mirrors to create the class-AB behavior in the first and second stage...A novel low-voltage two-stage operational amplifier employing class-AB architecture is presented. The structure utilizes level-shifters and current mirrors to create the class-AB behavior in the first and second stages. With this structure, the transconductances of the two stages are double compared with the normal configuration without class-AB behaviors with the same current consumption. Thus power can be saved and the operation frequency can be increased. The nested cascode miller compensation and symmetric common-mode feedback circuits are used for large unit-gain bandwidth, good phase margin and stability. Simulation results show that the sample-and-hold of the 12-bit 40-Ms/s pipelined ADC using the proposed amplifier consumes only 5.8 mW from 1.2 V power supply with signal-to-noise-and-distortion ratio 89.5 dB, spurious-free dynamic range 95.7 dB and total harmonic distortion -94.3 dB with Nyquist input signal frequency.展开更多
基金Project supported by the National High Technology Research and Development Program of China(No.2008AA010702)
文摘A12-Bit 40-MS/s pipelined analog-to-digital converter （ADC） incorporates a front-end RC constant matching technique and a set of front-end timing with different duty cycle that are beneficial for enhancing linearity in SHA-less architecture without tedious verification in back-end layout simulation. Employing SHA-less, opampsharing and low-power opamps for low dissipation and low cost, designed in 0.13μm CMOS technology, the prototype digitizes a 10.2-MHz input with 78.2-dB of spurious free dynamic range, 60.5-dB of signal-to-noise- and-distortion ratio, and -75.5-dB of total harmonic distortion （the first 5 harmonics included） while consuming 15.6-mW from a 1.2-V supply.
文摘A novel low-voltage two-stage operational amplifier employing class-AB architecture is presented. The structure utilizes level-shifters and current mirrors to create the class-AB behavior in the first and second stages. With this structure, the transconductances of the two stages are double compared with the normal configuration without class-AB behaviors with the same current consumption. Thus power can be saved and the operation frequency can be increased. The nested cascode miller compensation and symmetric common-mode feedback circuits are used for large unit-gain bandwidth, good phase margin and stability. Simulation results show that the sample-and-hold of the 12-bit 40-Ms/s pipelined ADC using the proposed amplifier consumes only 5.8 mW from 1.2 V power supply with signal-to-noise-and-distortion ratio 89.5 dB, spurious-free dynamic range 95.7 dB and total harmonic distortion -94.3 dB with Nyquist input signal frequency.
