A high performance 10-bit 100-MS/s two-channel time-interleaved pipelined ADC is designed for intermediate frequency 3G receivers,and OTA is shared among the channels for low power dissipation.Offset mismatch, gain mi...A high performance 10-bit 100-MS/s two-channel time-interleaved pipelined ADC is designed for intermediate frequency 3G receivers,and OTA is shared among the channels for low power dissipation.Offset mismatch, gain mismatch and time skew mismatch are overcome by OTA sharing,increasing the accuracy of each channel and global passive sampling respectively.The linearity deterioration caused by the charge injection of the output switch and the crosstalk of the off-switch capacitor is removed by modifying the clock signal arrangement.The total power consumption of the presented ADC is 70 mW from a 3.3-V power supply.Fabricated in a 180-nm CMOS process,the core of the prototype occupies an area of 2.5×1.5 mm;,achieving more than 70-dB spurious-free dynamic range and over 56-dB signal-to-noise distortion ratio over the Nyquist input band at 100-MHz sampling frequency.展开更多
This paper describes a 12-bit, 40-MS/s pipelined A/D converter （ADC） which is implemented in 0.18-μm CMOS process drawing 76-mW power from 3.3-V supply. Multi-bit architectures as well as telescopic operational tra...This paper describes a 12-bit, 40-MS/s pipelined A/D converter （ADC） which is implemented in 0.18-μm CMOS process drawing 76-mW power from 3.3-V supply. Multi-bit architectures as well as telescopic operational transconductance amplifiers （OTAs） are adopted in all pipeline stages for good power efficiency. In the first two stages, particularly, 3-bit/stage architectures are used to improve the ADC＇s linearity performance. The ADC is calibration-free and achieves a DNL of less than 0.51 LSB and an INL of less than 1 LSB. The SNDR performance is above 67 dB below Nyquist. The 80-dB SFDR performance is maintained within 1 dB for input frequencies up to 49 MHz at full sampling rate.展开更多
基金supported by the National Natural Science Foundation of China(No.90707002)
文摘A high performance 10-bit 100-MS/s two-channel time-interleaved pipelined ADC is designed for intermediate frequency 3G receivers,and OTA is shared among the channels for low power dissipation.Offset mismatch, gain mismatch and time skew mismatch are overcome by OTA sharing,increasing the accuracy of each channel and global passive sampling respectively.The linearity deterioration caused by the charge injection of the output switch and the crosstalk of the off-switch capacitor is removed by modifying the clock signal arrangement.The total power consumption of the presented ADC is 70 mW from a 3.3-V power supply.Fabricated in a 180-nm CMOS process,the core of the prototype occupies an area of 2.5×1.5 mm;,achieving more than 70-dB spurious-free dynamic range and over 56-dB signal-to-noise distortion ratio over the Nyquist input band at 100-MHz sampling frequency.
基金supported by the National Natural Science Foundation of China(No.60976032).
文摘This paper describes a 12-bit, 40-MS/s pipelined A/D converter （ADC） which is implemented in 0.18-μm CMOS process drawing 76-mW power from 3.3-V supply. Multi-bit architectures as well as telescopic operational transconductance amplifiers （OTAs） are adopted in all pipeline stages for good power efficiency. In the first two stages, particularly, 3-bit/stage architectures are used to improve the ADC＇s linearity performance. The ADC is calibration-free and achieves a DNL of less than 0.51 LSB and an INL of less than 1 LSB. The SNDR performance is above 67 dB below Nyquist. The 80-dB SFDR performance is maintained within 1 dB for input frequencies up to 49 MHz at full sampling rate.
