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Novel layout design of 4H-SiC merged PiN Schottky diodes leading to improved surge robustness
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作者 陈嘉豪 王颖 +2 位作者 费新星 包梦恬 曹菲 《Chinese Physics B》 SCIE EI CAS CSCD 2023年第9期552-558,共7页
A method to improve the surge current capability of silicon carbide(SiC)merged PiN Schottky(MPS)diodes is presented and investigated via three-dimensional electro-thermal simulations.When compared with a conventional ... A method to improve the surge current capability of silicon carbide(SiC)merged PiN Schottky(MPS)diodes is presented and investigated via three-dimensional electro-thermal simulations.When compared with a conventional MPS diode,the proposed structure has a more uniform current distribution during bipolar conduction due to the help of the continuous P+surface,which can avoid the formation of local hotspots during the surge process.The Silvaco simulation results show that the proposed structure has a 20.29%higher surge capability and a 15.06%higher surge energy compared with a conventional MPS diode.The bipolar on-state voltage of the proposed structure is 4.69 V,which is 56.29%lower than that of a conventional MPS diode,enabling the device to enter the bipolar mode earlier during the surge process.Furthermore,the proposed structure can suppress the occurrence of‘snapback'phenomena when switching from the unipolar to the bipolar operation mode.In addition,an analysis of the surge process of MPS diodes is carried out in detail. 展开更多
关键词 merged PiN Schottky(MPS)diode silicon carbide(SiC) surge capability surge energy reliability
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Simulation study of high voltage GaN MISFETs with embedded PN junction
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作者 Xin-Xing Fei Ying Wang +1 位作者 Xin Luo Cheng-Hao Yu 《Chinese Physics B》 SCIE EI CAS CSCD 2020年第8期198-203,共6页
In this paper,we propose a new enhanced GaN MISFET with embedded pn junction,i.e.,EJ-MISFET,to enhance the breakdown voltage.The embedded pn junction is used to improve the simulated device electric field distribution... In this paper,we propose a new enhanced GaN MISFET with embedded pn junction,i.e.,EJ-MISFET,to enhance the breakdown voltage.The embedded pn junction is used to improve the simulated device electric field distribution between gate and drain,thus achieving an enhanced breakdown voltage(BV).The proposed simulated device with LGD=15μm presents an excellent breakdown voltage of 2050 V,which is attributed to the improvement of the device electric field distribution between gate and drain.In addition,the ON-resistance(RON)of 15.37Ω·mm and Baliga's figure of merit of 2.734 GW·cm-2 are achieved in the optimized EJ-MISFET.Compared with the field plate conventional GaN MISFET(FPC-MISFET)without embedded pn junction structure,the proposed simulated device increases the BV by 32.54%and the Baliga's figure of merit is enhanced by 71.3%. 展开更多
关键词 TCAD Baliga’s figure of merit(BFOM) breakdown voltage(BV)
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