A Novel Power Supply Solution of a Passive RFID Transponder

This paper presents a power supply solution for fully integrated passive radio-frequency identification （RFID） transponder IC, which has been implemented in 0.35μm CMOS technology with embedded EEPROM from Chartered Semiconductor. The proposed AC/DC and DC/DC charge pumps can generate stable output for RFID applications with quite low power dissipation and extremely high pumping efficiency. An analytical model of the voltage multiplier, comparison with other charge pumps, simulation results, and chip testing results are presented.

A Low Power Dissipation Wide-Band CMOS Frequency Synthesizer for a Dual-Band GPS Receiver

This paper presents a wide tuning range CMOS frequency synthesizer for a dual-band GPS receiver,which has been fabricated in a standard 0.18μm RF CMOS process. With a high Q on-chip inductor, the wide-band VCO shows a tuning range from 2 to 3.6GHz to cover 2.45 and 3.14GHz in case of process corner or temperature variation,with a current consumption varying accordingly from 0.8 to 0.4mA,from a 1.8V supply voltage. Measurement results show that the whole frequency synthesizer consumes very low power of 5.6mW working at L1 band with in-band phase noise less than - 82dBc/Hz and out-of-band phase noise about - ll2dBc/Hz at 1MHz offset from a 3. 142GHz carrier. The performance of the frequency synthesizer meets the requirements of GPS applications very well.

Design of an Active-RC Low-Pass Filter with Accurate Tuning Architecture

An active-RC low-pass filter of 5MHz cutoff frequency with a tuning architecture is proposed. It is implemented in 0. 18μm standard CMOS technology. The accuracy of the tuning system is improved to be within （ - 1.24%, ＋ 2.16%） in measurement. The chip area of the tuning system is only a quarter of that of the main-filter. After tuning is completed, the tuning system will be turned off automatically to save power and to avoid interference. The in-band 3rd order harmonic input intercept point （IIP3） is larger than 16. ldBm, with 50Ω as the source impedance. The input referred noise is about 36μVrms The measured group delay variation of the filter between 3 and 5MHz is only 24ns,and the filter power consump- tion is 3.6roW. This filter with the tuning system is realized easily and can be used in many wireless low-IF receiver applications, such as global position systems （GPS）, global system for mobile communications （GSM） and code division multiple access （CDMA） chips.

A self-biased PLL with low power and compact area

A new low power, low phase jitter, compact realization, and sell-biased PLL, which is fabricated on SMIC 40 nm CMOS technology is introduced. The proposed self-biased PLL eliminates extra band gap biasing circuits, and internally generates all the biasing voltages and currents. Meanwhile, all of the PLL dynamic loop parameters, such as loop bandwidth, natural frequency, damping factors are kept constant adaptively. By optimizing the circuit structures, the perfect unity of chip estate, power dissipation, phase jitter, and loop stability is achieved. THe PLL consumes 4.2 mW of power tinder 1.1 V/2.5 V voltage supply at 2.4 GHz VCO frequency, while occupying a die area of less than 0.02 mmz （180 × 110 μm2）, and the typical period jitter （RMS） is around 2.8 ps.

An asymmetric MOSFET-C band-pass filter with on-chip charge pump auto-tuning

An asymmetric MOSFET-C band-pass filter （BPF） with on chip charge pump auto-tuning is presented. It is implemented in UMC （United Manufacturing Corporation） 0.18 μm CMOS process technology. The filter system with auto-tuning uses a master-slave technique for continuous tuning in which the charge pump outputs 2.663 V, much higher than the power supply voltage, to improve the linearity of the filter. The main filter with third order low-pass and second order high-pass properties is an asymmetric band-pass filter with bandwidth of 2.730-5.340 MHz. The in-band third order harmonic input intercept point （ⅡP3） is 16.621 dBm, with 50Ω as the source impedance. The input referred noise is about 47.455 μVrms. The main filter dissipates 3.528 mW while the auto-tuning system dissipates 2.412 mW from a 1.8 V power supply. The filter with the auto-tuning system occupies 0.592 mm2 and it can be utilized in GPS （global positioning system） and Bluetooth systems.

A 0.13μm CMOS Δ ∑ fractional-N frequency synthesizer for WLAN transceivers

A fractional-N frequency synthesizer fabricated in a 0.13μm CMOS technology is presented for the application of IEEE 802.11 b/g wireless local area network（WLAN） transceivers.A monolithic LC voltage controlled oscillator（VCO） is implemented with an on-chip symmetric inductor.The fractional-TV frequency divider consists of a pulse swallow frequency divider and a 3rd-order multistage noise shaping（MASH）△Σmodulator with noise-shaped dithering techniques.Measurement results show that in all channels,phase noise of the synthesizer achieves -93 dBc/Hz and -118 dBc/Hz in band and out of band respectively with a phase-frequency detector （PFD） frequency of 20 MHz and a loop bandwidth of 100 kHz.The integrated RMS phase error is no more than 0.8°.The proposed synthesizer consumes 8.4 mW from a 1.2 V supply and occupies an area of 0.86 mm^2.

A high-performance low-power CMOS AGC for GPS application

A wide tuning range,low power CMOS automatic gain control（AGC） with a simple architecture is proposed. The proposed AGC is composed of a variable gain amplifier（VGA）,a comparator and a charge pump,and the dB-linear gain is controlled by the charge pump.The AGC was implemented in a 0.18μm CMOS technology.The dynamic range of the VGA is more than 55 dB,the bandwidth is 30 MHz,and the gain error is lower than±1.5 dB over the full temperature and gain ranges.It is designed for GPS application and is fed from a single 1.8 V power supply. The AGC power consumption is less than 5 mW,and the area of the AGC is 700×450μm^2.