Digital calibration and control techniques for narrow band integrated low-IF receivers with on-chip frequency synthesizer are presented.The calibration and control system,which is adopted to ensure an achievable signa...Digital calibration and control techniques for narrow band integrated low-IF receivers with on-chip frequency synthesizer are presented.The calibration and control system,which is adopted to ensure an achievable signal-to-noise ratio and bit error rate,consists of a digitally controlled,high resolution dB-linear automatic gain control（AGC）,an inphase（I） and quadrature（Q） gain and phase mismatch calibration,and an automatic frequency calibration（AFC） of a wideband voltage-controlled oscillator in a PLL based frequency synthesizer.The calibration system has a low design complexity with little power and small die area.Simulation results show that the calibration system can enlarge the dynamic range to 72 dB and minimize the phase and amplitude imbalance between I and Q to 0.08° and 0.024 dB,respectively,which means the image rejection ratio is better than 60 dB.In addition,the calibration time of the AFC is 1.12 μs only with a reference clock of 100 MHz.展开更多
A receiver for SRDs implemented by the 0.35μm CMOS process is presented. The receiver, together with the ADC, power amplifier （PA）, frequency synthesizer and digital baseband has been integrated into a single chip ...A receiver for SRDs implemented by the 0.35μm CMOS process is presented. The receiver, together with the ADC, power amplifier （PA）, frequency synthesizer and digital baseband has been integrated into a single chip solution. Low cost and low power requirements are met by optimizing the receiver architecture and circuit topology. A simple mixed-signal mode I/Q imbalance calibration circuit is proposed to enhance the IRR （image rejection ratio） so as to raise the BER. From a single 3 V power supply, the receiver consumes 5.9 mA. The measurement result shows that the receiver achieves reference sensitivity of-60 dBm and a control gain of 60 dB. The S11 reaches -20 dB at 433 MHz and -10 dB at 868 MHz without off-chip impedance match network. The die area is only 2 mm^2 including the bias circuit.展开更多
文摘Digital calibration and control techniques for narrow band integrated low-IF receivers with on-chip frequency synthesizer are presented.The calibration and control system,which is adopted to ensure an achievable signal-to-noise ratio and bit error rate,consists of a digitally controlled,high resolution dB-linear automatic gain control（AGC）,an inphase（I） and quadrature（Q） gain and phase mismatch calibration,and an automatic frequency calibration（AFC） of a wideband voltage-controlled oscillator in a PLL based frequency synthesizer.The calibration system has a low design complexity with little power and small die area.Simulation results show that the calibration system can enlarge the dynamic range to 72 dB and minimize the phase and amplitude imbalance between I and Q to 0.08° and 0.024 dB,respectively,which means the image rejection ratio is better than 60 dB.In addition,the calibration time of the AFC is 1.12 μs only with a reference clock of 100 MHz.
文摘A receiver for SRDs implemented by the 0.35μm CMOS process is presented. The receiver, together with the ADC, power amplifier （PA）, frequency synthesizer and digital baseband has been integrated into a single chip solution. Low cost and low power requirements are met by optimizing the receiver architecture and circuit topology. A simple mixed-signal mode I/Q imbalance calibration circuit is proposed to enhance the IRR （image rejection ratio） so as to raise the BER. From a single 3 V power supply, the receiver consumes 5.9 mA. The measurement result shows that the receiver achieves reference sensitivity of-60 dBm and a control gain of 60 dB. The S11 reaches -20 dB at 433 MHz and -10 dB at 868 MHz without off-chip impedance match network. The die area is only 2 mm^2 including the bias circuit.
