SiC高温氧化工艺开发和界面特性分析

将n型4H-Si C(0001)偏4°外延材料在1 200℃、1 250℃、1 300℃和1 350℃等4种温度条件下进行高温热氧化,生成SiO2薄膜;通过测试MOS电容结构的C-V和I-V特性,对Si O2/SiC界面特性进行了分析。结果表明,在1 350℃时,靠近导带处的界面态密度降低,这有助于生长较低缺陷的SiO2薄膜;同时,低于1 300℃时,测得SiO2薄膜击穿电场大于6 MV/cm,能满足SiC MOSFET器件的工作要求。

SiO2/4H-SiC界面氮化退火

通过1 300℃高温干氧热氧化法在n型4H-SiC外延片上生长了厚度为60 nm的SiO2栅氧化层。为了开发适合于生长低界面态密度和高沟道载流子迁移率的SiC MOSFET器件产品的栅极氧化层退火条件,研究了不同退火条件下的SiO2/SiC界面电学特性参数。制作了MOS电容和横向MOSFET器件,通过表征SiO2栅氧化层C-V特性和MOSFET器件I-V特性,提取平带电压、C-V磁滞电压、SiO2/SiC界面态密度和载流子沟道迁移率等电学参数。实验结果表明,干氧氧化形成SiO2栅氧化层后,在1 300℃通入N2退火30 min,随后在相同温度下进行NO退火120 min,为最佳栅极氧化层退火条件,此时,SiO2/SiC界面态密度能够降低至2.07×1012cm-2·e V^(-1)@0.2 e V,SiC MOSFET沟道载流子迁移率达到17 cm2·V^(-1)·s^(-1)。

MEBO治疗特异性溃疡108例体会

本文总结经门诊应用MEBO治疗因做结核菌素试验及接种卡介苗所致的前臂和上臂三角肌外侧皮下溃疡108例，收到满意效果。过去对此类溃疡多采用于结（涂龙胆紫）或药物湿敷疗法，经反复多次换药致使创面逐渐加深，久治不愈，多长达3～6个月，个别患者竟达一年之久，于1989年后改用MEBO外敷包扎治疗后7～15天大多数病人痊愈，个别患者20天左右也都能平皮愈合。这说明MEBO的湿润效应和自动引流净化创面，活血化瘀，去腐生肌的作用，促进了局部微循环而使创面早日愈合。

基于SiC基底的Y_2O_3/Al_2O_3堆栈MOS电容的特性研究

通过在n型碳化硅(SiC)晶圆上用物理气相沉积法(PVD)和原子层沉积法(ALD)分别沉积Y_2O_3介质和Al_2O_3,形成金属/Al_2O_3/Y_2O_3/SiC高k介质堆栈结构MOS电容。X射线光电子能谱(XPS)分析研究Al_2O_3/Y_2O_3堆栈结构氧化层介质之间以及氧化层与SiC晶圆之间的相互扩散和反应关系;研究不同金属电极MOS电容的C-V特性,Ni电极MOS电容具有良好的稳定性,对介质层的相对介电常数影响最小,Mg电极MOS电容的理想平带电压最小,同时氧化层陷阱密度最小;随着C-V测试频率的降低,氧化层电容Cox逐渐增加,Al_2O_3/Y_2O_3介质层的相对介电常数逐渐增大,等效氧化层厚度(EOT)减小,平带电容电压减小。

4H-SiC栅氧氮化工艺优化

为了改善SiC MOS电容氧化膜的质量和界面态密度,采用正交试验法考察了温度、压力、时间以及一氧化氮气流量等主要氮化工艺参数对4H-SiC MOS电容栅氧特性的影响,发现温度是影响栅氧特性最关键因素。优选出栅氧的最佳氮化工艺条件,并找到氮化工艺条件对击穿电压和界面态密度的影响规律。

利福平溶液剂治疗脂溢性皮炎

脂溢性皮炎,以往药物治疗,效果不够理想。我们用利福平溶液剂涂搽治疗脂溢性皮炎30例,取得极为满意的疗效。1 病例与治疗方法患者30例,均经省级医院皮肤科确诊为脂溢性皮炎。其中男性22例,女性8例;病程2mo～5y 不等;皮疹多以头皮、颈面及前后发际多见。严重者则满头面颈遍布斑斑点点,其中一例严重者某些部位皮疹连片,枕部因抓搔而感染,流淌淡黄粘液。

Effect of NO annealing on charge traps in oxide insulator and transition layer for 4H-SiC metal–oxide–semiconductor devices

The effect of nitric oxide（NO） annealing on charge traps in the oxide insulator and transition layer in n-type4H–Si C metal–oxide–semiconductor（MOS） devices has been investigated using the time-dependent bias stress（TDBS）,capacitance–voltage（C–V）,and secondary ion mass spectroscopy（SIMS）.It is revealed that two main categories of charge traps,near interface oxide traps（Nniot） and oxide traps（Not）,have different responses to the TDBS and C–V characteristics in NO-annealed and Ar-annealed samples.The Nniotare mainly responsible for the hysteresis occurring in the bidirectional C–V characteristics,which are very close to the semiconductor interface and can readily exchange charges with the inner semiconductor.However,Not is mainly responsible for the TDBS induced C–V shifts.Electrons tunneling into the Not are hardly released quickly when suffering TDBS,resulting in the problem of the threshold voltage stability.Compared with the Ar-annealed sample,Nniotcan be significantly suppressed by the NO annealing,but there is little improvement of Not.SIMS results demonstrate that the Nniotare distributed within the transition layer,which correlated with the existence of the excess silicon.During the NO annealing process,the excess Si atoms incorporate into nitrogen in the transition layer,allowing better relaxation of the interface strain and effectively reducing the width of the transition layer and the density of Nniot.

Near-interface oxide traps in 4H–SiC MOS structures fabricated with and without annealing in NO

Near-interface oxide traps （NIOTs） in 4H-SiC metal-oxide-semiconductor （MOS） structures fabricated with and without annealing in NO are systematically investigated in this paper. The properties of NIOTs in SiC MOS structures prepared with and without annealing in NO are studied and compared in detail. Two main categories of the NIOTs, the “slow” and “fast” NIOTs, are revealed and extracted. The densities of the “fast” NIOTs are determined to be 0.761011 cm-2 and 0.471011 cm-2 for the N2 post oxidation annealing （POA） sample and NO POA sample, respectively. The densities of “slow” NIOTs are 0.791011 cm-2 and 9.441011 cm-2 for the NO POA sample and N2 POA sample, respectively. It is found that the NO POA process only can significantly reduce “slow” NIOTs. However, it has a little effect on “fast” NIOTs. The negative and positive constant voltage stresses （CVS） reveal that electrons captured by those “slow” NIOTs and bulk oxide traps （BOTs） are hardly emitted by the constant voltage stress.

防止计划生育手术和妇查中的交叉感染

目前由于种种原因,传染性疾病(淋病、滴虫、尖锐湿疣等)发病率很高,并已开始传播、蔓延。在妇科检查中时常发生医源性交叉感染。因此防止交叉感染尤为重要。近年来我们把预防交叉感染做为一项重要的工作,在我们医院小、条件差的情况下,采取了行之有效的控制感染的预防措施,建立健全了各种消毒隔离制度,收到了良好的效果。 我们的具体作法是:门诊设置三室二台,下班前检查台要彻底洗刷并用紫外线照射消毒。

Characterization of the effects of nitrogen and hydrogen passivation on SiO2/4H-SiC interface by low temperature conductance measurements

We investigate the effects of NO annealing and forming gas （FG） annealing on the electrical properties of a SiO2/SiC interface by low-temperature conductance measurements. With nitrogen passivation, the density of interface states （DIT） is significantly reduced in the entire energy range, and the shift of flatband voltage, AVFB, is effectively suppressed to less than 0.4 V. However, very fast states are observed after NO annealing and the response frequencies are higher than 1 MHz at room temperature. After additional FG annealing, the DIT and AVFB are further reduced. The values of the DIT decrease to less than 1011 cm-2 eV- 1 for the energy range of Ec - ET 〉/0.4 eV. It is suggested that the fast states in shallow energy levels originated from the N atoms accumulating at the interface by NO annealing. Though FG annealing has a limited effect on these shallow traps, hydrogen can terminate the residual Si and C dangling bonds corresponding to traps at deep energy levels and improve the interface quality further. It is indicated that NO annealing in conjunction with FG annealing will be a better post-oxidation process method for high performance SiC MOSFETs.

Effect of post oxidation annealing in nitric oxide on interface properties of 4H-SiC/SiO_2 after high temperature oxidation

The interface properties of 4H-SiC metal oxide semiconductor （MOS） capacitors with post-oxidation annealing （POA） in nitric oxide （NO） ambient after high temperature （1300 ℃） oxidation have been investigated using capacitance-voltage （C V） measurements. The experimental results show that the interface states density （Dit） can be obviously decreased by the POA in NO ambient （NO-POA） and further reduced with increasing POA temperature and time. In the meantime significant reduction of the interface states density and oxidation time can be achieved at the higher thermal oxidation temperature, which results in the better oxide MOS characteristics and lower production costs. The dependence of Dit on POA temperature and time has been also discussed in detail.