UM-BUS(Uniform Model Bus)总线是面向嵌入式系统的具有远程存储能力的可重构高速串行总线.它支持多个节点之间直接互连,可以根据链路状态将数据包动态地分配到通信通道上进行高可靠并行高速传输.随着嵌入式系统处理器频率和传输速率的...UM-BUS(Uniform Model Bus)总线是面向嵌入式系统的具有远程存储能力的可重构高速串行总线.它支持多个节点之间直接互连,可以根据链路状态将数据包动态地分配到通信通道上进行高可靠并行高速传输.随着嵌入式系统处理器频率和传输速率的提升,功耗问题已经成为制约嵌入式系统发展的重要瓶颈之一.针对UM-BUS总线系统,本文将系统的功耗优化问题形式化描述为整形线性规划问题,通过求解最优的消息调度方法使得总线上各通道公共空闲时间最大化,从而可在该空闲时间内使相关节点以低功耗模式运行,优化系统的总体功耗.本文还提出一种启发式算法来简化求解该调度问题.实验结果表明,对于给定的传输任务,启发式算法和线性最优算法能增加系统最大空闲时间平均达40.38%和47.48%,从而降低了52.04%和57.74%系统功耗.展开更多
The particles-induced soft errors are a major threat to the reliability of microprocessors. Even worse,multi-bits upsets（MBUs） are ever-increased due to the rapidly shrinking feature size of the IC on a chip. Severa...The particles-induced soft errors are a major threat to the reliability of microprocessors. Even worse,multi-bits upsets（MBUs） are ever-increased due to the rapidly shrinking feature size of the IC on a chip. Several architecture-level mechanisms have been proposed to protect microprocessors from soft errors, such as dual and triple modular redundancies（DMR and TMR）. However, most of them are inefficient to combat the growing multibits errors or cannot well balance the critical paths delay, area and power penalty. This paper proposes a novel architecture, self-recovery dual-pipeline（SRDP）, to effectively provide soft error detection and recovery with low cost for general RISC structures. We focus on the following three aspects. First, an advanced DMR pipeline is devised to detect soft error, especially MBU. Second, SEU/MBU errors can be located by enhancing self-checking logic into pipelines stage registers. Third, a recovery scheme is proposed with a recovery cost of 1 or 5 clock cycles.Our evaluation of a prototype implementation exhibits that the SRDP can successfully detect particle-induced soft errors up to 100% and recovery is nearly 95%, the other 5% will inter a specific trap.展开更多
文摘UM-BUS(Uniform Model Bus)总线是面向嵌入式系统的具有远程存储能力的可重构高速串行总线.它支持多个节点之间直接互连,可以根据链路状态将数据包动态地分配到通信通道上进行高可靠并行高速传输.随着嵌入式系统处理器频率和传输速率的提升,功耗问题已经成为制约嵌入式系统发展的重要瓶颈之一.针对UM-BUS总线系统,本文将系统的功耗优化问题形式化描述为整形线性规划问题,通过求解最优的消息调度方法使得总线上各通道公共空闲时间最大化,从而可在该空闲时间内使相关节点以低功耗模式运行,优化系统的总体功耗.本文还提出一种启发式算法来简化求解该调度问题.实验结果表明,对于给定的传输任务,启发式算法和线性最优算法能增加系统最大空闲时间平均达40.38%和47.48%,从而降低了52.04%和57.74%系统功耗.
文摘The particles-induced soft errors are a major threat to the reliability of microprocessors. Even worse,multi-bits upsets（MBUs） are ever-increased due to the rapidly shrinking feature size of the IC on a chip. Several architecture-level mechanisms have been proposed to protect microprocessors from soft errors, such as dual and triple modular redundancies（DMR and TMR）. However, most of them are inefficient to combat the growing multibits errors or cannot well balance the critical paths delay, area and power penalty. This paper proposes a novel architecture, self-recovery dual-pipeline（SRDP）, to effectively provide soft error detection and recovery with low cost for general RISC structures. We focus on the following three aspects. First, an advanced DMR pipeline is devised to detect soft error, especially MBU. Second, SEU/MBU errors can be located by enhancing self-checking logic into pipelines stage registers. Third, a recovery scheme is proposed with a recovery cost of 1 or 5 clock cycles.Our evaluation of a prototype implementation exhibits that the SRDP can successfully detect particle-induced soft errors up to 100% and recovery is nearly 95%, the other 5% will inter a specific trap.
