A low jitter,low spur multiphase phase-locked loop（PLL） for an impulse radio ultra-wideband（IR-UWB） receiver is presented.The PLL is based on a ring oscillator in order to simultaneously meet the jitter requiremen...A low jitter,low spur multiphase phase-locked loop（PLL） for an impulse radio ultra-wideband（IR-UWB） receiver is presented.The PLL is based on a ring oscillator in order to simultaneously meet the jitter requirement, low power consumption and multiphase clock output.In this design,a noise and matching improved voltage-controlled oscillator（VCO） is devised to enhance the timing accuracy and phase noise performance of multiphase clocks.By good matching achieved in the charge pump and careful choice of the loop filter bandwidth,the reference spur is suppressed. A phase noise of-118.42 dBc/Hz at a frequency offset of 1 MHz,RMS jitter of 1.53 ps and reference spur of-66.81 dBc are achieved at a carrier frequency of 264 MHz in measurement.The chip was manufactured in 0.13μm CMOS technology and consumes 4.23 mW from a 1.2 V supply while occupying 0.14 mm^2 area.展开更多
A high speed sampler for a sub-sampling impulse radio UWB receiver is presented. In this design, the sampler uses a time-interleaved topology with a single track and hold circuit, full custom clock generator, and off-...A high speed sampler for a sub-sampling impulse radio UWB receiver is presented. In this design, the sampler uses a time-interleaved topology with a single track and hold circuit, full custom clock generator, and off- set cancelled comparator. These three main blocks are also discussed and analyzed. The circuit was fabricated in 0.13 μm CMOS technology. Measurement results indicate that the sampler achieves a maximum 3 GS/s sampling rate. The power consumption of the sampler is 27 mW under a supply voltage of 1.2 V. The total chip area including pads is 1.4 × 0.97 mm^2.展开更多
This paper presents a novel,fully integrated transmitter for 3-5 GHz pulsed UWB.The BPSK modulation transmitter has been implemented in SMIC CMOS 0.13μm technology with a 1.2-V supply voitage and a die size of 0.8...This paper presents a novel,fully integrated transmitter for 3-5 GHz pulsed UWB.The BPSK modulation transmitter has been implemented in SMIC CMOS 0.13μm technology with a 1.2-V supply voitage and a die size of 0.8×0.95 mm;.This transmitter is based on the impulse response filter method,which uses a tunable R paralleled with a LC frequency selection network to realize continuously adjustable pulse parameters,including bandwidth,width and amplitude.Due to the extremely low duty of the pulsed UWB,a proposed output buffer is employed to save power consumption significantly.Finally,measurement results show that the transmitter consumes only 16.3 pJ/pulse to achieve a pulse repetition rate of 100 Mb/s.Generated pulses strictly comply with the FCC spectral mask.The continuously variable pulse width is from 900 to 1.5 ns and the amplitude with the minimum 178 mVpp and the maximum 432 mVpp can be achieved.展开更多
A 4224 MHz phase-locked loop （PLL） is implemented in 0.13 μm CMOS technology. A dynamic phase frequency detector is employed to shorten the delay reset time so as to minimize the noise introduced by the charge pump...A 4224 MHz phase-locked loop （PLL） is implemented in 0.13 μm CMOS technology. A dynamic phase frequency detector is employed to shorten the delay reset time so as to minimize the noise introduced by the charge pump. Dynamic mismatch of charge pump is considered. By balancing the switch signals of the charge pump, a good dynamic matching characteristic is achieved. A high-speed digital frequency divider with balanced input load is also designed to improve in-band phase noise performance. The 4224 MHz PLL achieves phase noises of-94 dBc/Hz and -114.4 dBc/Hz at frequency offsets of 10 kHz and 1 MHz, respectively. The integrated RMS jitter of the PLL is 0.57 ps （100 Hz to 100 MHz） and the PLL has a reference spur of-63 dB with the second order passive low pass filter.展开更多
基金Project supported by the National High Technology Research and Development Program of China(No.2009AA01Z261)the State Key Laboratory of Wireless Telecommunication,Southeast University,China.
文摘A low jitter,low spur multiphase phase-locked loop（PLL） for an impulse radio ultra-wideband（IR-UWB） receiver is presented.The PLL is based on a ring oscillator in order to simultaneously meet the jitter requirement, low power consumption and multiphase clock output.In this design,a noise and matching improved voltage-controlled oscillator（VCO） is devised to enhance the timing accuracy and phase noise performance of multiphase clocks.By good matching achieved in the charge pump and careful choice of the loop filter bandwidth,the reference spur is suppressed. A phase noise of-118.42 dBc/Hz at a frequency offset of 1 MHz,RMS jitter of 1.53 ps and reference spur of-66.81 dBc are achieved at a carrier frequency of 264 MHz in measurement.The chip was manufactured in 0.13μm CMOS technology and consumes 4.23 mW from a 1.2 V supply while occupying 0.14 mm^2 area.
基金supported by the National High Technology Research and Development Program of China(No.2009AA01Z261)the State Key Laboratory of Wireless Telecommunication,Southeast University.
文摘A high speed sampler for a sub-sampling impulse radio UWB receiver is presented. In this design, the sampler uses a time-interleaved topology with a single track and hold circuit, full custom clock generator, and off- set cancelled comparator. These three main blocks are also discussed and analyzed. The circuit was fabricated in 0.13 μm CMOS technology. Measurement results indicate that the sampler achieves a maximum 3 GS/s sampling rate. The power consumption of the sampler is 27 mW under a supply voltage of 1.2 V. The total chip area including pads is 1.4 × 0.97 mm^2.
基金Project supported by the National High Technology Research and Development of China(No2009AA01Z261)the State Key Laboratory of Wireless Telecommunication,Southeast University,China
文摘This paper presents a novel,fully integrated transmitter for 3-5 GHz pulsed UWB.The BPSK modulation transmitter has been implemented in SMIC CMOS 0.13μm technology with a 1.2-V supply voitage and a die size of 0.8×0.95 mm;.This transmitter is based on the impulse response filter method,which uses a tunable R paralleled with a LC frequency selection network to realize continuously adjustable pulse parameters,including bandwidth,width and amplitude.Due to the extremely low duty of the pulsed UWB,a proposed output buffer is employed to save power consumption significantly.Finally,measurement results show that the transmitter consumes only 16.3 pJ/pulse to achieve a pulse repetition rate of 100 Mb/s.Generated pulses strictly comply with the FCC spectral mask.The continuously variable pulse width is from 900 to 1.5 ns and the amplitude with the minimum 178 mVpp and the maximum 432 mVpp can be achieved.
基金supported by the National High Technology Research and Development Program of China(No.SQ2008AA01Z4473469).
文摘A 4224 MHz phase-locked loop （PLL） is implemented in 0.13 μm CMOS technology. A dynamic phase frequency detector is employed to shorten the delay reset time so as to minimize the noise introduced by the charge pump. Dynamic mismatch of charge pump is considered. By balancing the switch signals of the charge pump, a good dynamic matching characteristic is achieved. A high-speed digital frequency divider with balanced input load is also designed to improve in-band phase noise performance. The 4224 MHz PLL achieves phase noises of-94 dBc/Hz and -114.4 dBc/Hz at frequency offsets of 10 kHz and 1 MHz, respectively. The integrated RMS jitter of the PLL is 0.57 ps （100 Hz to 100 MHz） and the PLL has a reference spur of-63 dB with the second order passive low pass filter.
