目的观察靳三针联合改良强制性运动疗法对痉挛型脑瘫患者运动功能的影响。方法将80例痉挛型脑瘫患者按简单随机法分为观察组和对照组,每组40例。两组患者均行基础康复治疗,对照组另予改良强制性运动疗法,观察组在对照组治疗基础上予靳...目的观察靳三针联合改良强制性运动疗法对痉挛型脑瘫患者运动功能的影响。方法将80例痉挛型脑瘫患者按简单随机法分为观察组和对照组,每组40例。两组患者均行基础康复治疗,对照组另予改良强制性运动疗法,观察组在对照组治疗基础上予靳三针针刺治疗。比较两组治疗前后Peabody运动发育量表-2(Peabody development motor scale-2,PDMS-2)、粗大运动功能评定量表(gross motor function scale,GMFM)和儿童平衡量表(pediatric balance scale,PBS)的评分变化以及跨步长度、10 m步行时间和1 min步行距离的变化。结果PDMS-2视觉运动整合(visual motor integration,VMI)维度评分组内效应(F时点、F交互)及组间效应(F组间)比较,差异有统计学意义(P<0.05);两组不同时间点VMI评分比较,差异有统计学意义(P<0.05);治疗前,两组VMI评分比较,差异无统计学意义(P>0.05);治疗1个月和治疗3个月,观察组VMI评分明显高于对照组(P<0.05)。治疗后,观察组D区和E区GMFM评分和PBS评分高于对照组(P<0.05),跨步长度和1 min步行距离大于对照组(P<0.05),10 m步行时间短于对照组(P<0.05)。结论在基础康复治疗上,靳三针联合改良强制性运动疗法可显著改善痉挛型脑瘫患者的平衡能力,提高患者运动功能与步行能力,效果优于单纯改良强制性运动疗法。展开更多
This paper presents an ultra-low power incremental ADC for biosensor interface circuits. The ADC consists of a resettable second-order delta-sigma （△ ∑） modulator core and a resettable decimation filter. Several t...This paper presents an ultra-low power incremental ADC for biosensor interface circuits. The ADC consists of a resettable second-order delta-sigma （△ ∑） modulator core and a resettable decimation filter. Several techniques are adopted to minimize its power consumption. A feedforward path is introduced to the modulator core to relax the signal swing and linearity requirement of the integrators. A correlated-double-sampling （CDS） technique is applied to reject the offset and 1/f noise, thereby removing the integrator leakage and relaxing the gain requirement of the OTA. A simple double-tailed inverter-based fully differential OTA using a thick-oxide CMOS is proposed to operate in the subthreshold region to fulfill both an ultra-low power and a large output swing at 1.2 V supply. The signal addition before the comparator in the feedforward architecture is performed in the current domain instead of the voltage domain to minimize the capacitive load to the integrators. The capacitors used in this design are of customized metal-oxide metal （MOM） type to reach the minimum capacitance set by the k T~ C noise limit. Fabricated with a 1P6M 0.18/zm CMOS technology, the presented incremental ADC consumes 600 nW at 2 kS/s from a 1.2 V supply, and achieves 68.3 dB signal to noise and distortion ratio （SNDR） at the Nyquist frequency and an FOM of 0.14 pJ/conversion step. The core area is 100 × 120 μm^2.展开更多
文摘目的观察靳三针联合改良强制性运动疗法对痉挛型脑瘫患者运动功能的影响。方法将80例痉挛型脑瘫患者按简单随机法分为观察组和对照组,每组40例。两组患者均行基础康复治疗,对照组另予改良强制性运动疗法,观察组在对照组治疗基础上予靳三针针刺治疗。比较两组治疗前后Peabody运动发育量表-2(Peabody development motor scale-2,PDMS-2)、粗大运动功能评定量表(gross motor function scale,GMFM)和儿童平衡量表(pediatric balance scale,PBS)的评分变化以及跨步长度、10 m步行时间和1 min步行距离的变化。结果PDMS-2视觉运动整合(visual motor integration,VMI)维度评分组内效应(F时点、F交互)及组间效应(F组间)比较,差异有统计学意义(P<0.05);两组不同时间点VMI评分比较,差异有统计学意义(P<0.05);治疗前,两组VMI评分比较,差异无统计学意义(P>0.05);治疗1个月和治疗3个月,观察组VMI评分明显高于对照组(P<0.05)。治疗后,观察组D区和E区GMFM评分和PBS评分高于对照组(P<0.05),跨步长度和1 min步行距离大于对照组(P<0.05),10 m步行时间短于对照组(P<0.05)。结论在基础康复治疗上,靳三针联合改良强制性运动疗法可显著改善痉挛型脑瘫患者的平衡能力,提高患者运动功能与步行能力,效果优于单纯改良强制性运动疗法。
基金supported by the National Natural Science Foundation of China(No.61204033) the Science and Technology Commission of Shanghai Municipality(No.13511500200)
文摘This paper presents an ultra-low power incremental ADC for biosensor interface circuits. The ADC consists of a resettable second-order delta-sigma （△ ∑） modulator core and a resettable decimation filter. Several techniques are adopted to minimize its power consumption. A feedforward path is introduced to the modulator core to relax the signal swing and linearity requirement of the integrators. A correlated-double-sampling （CDS） technique is applied to reject the offset and 1/f noise, thereby removing the integrator leakage and relaxing the gain requirement of the OTA. A simple double-tailed inverter-based fully differential OTA using a thick-oxide CMOS is proposed to operate in the subthreshold region to fulfill both an ultra-low power and a large output swing at 1.2 V supply. The signal addition before the comparator in the feedforward architecture is performed in the current domain instead of the voltage domain to minimize the capacitive load to the integrators. The capacitors used in this design are of customized metal-oxide metal （MOM） type to reach the minimum capacitance set by the k T~ C noise limit. Fabricated with a 1P6M 0.18/zm CMOS technology, the presented incremental ADC consumes 600 nW at 2 kS/s from a 1.2 V supply, and achieves 68.3 dB signal to noise and distortion ratio （SNDR） at the Nyquist frequency and an FOM of 0.14 pJ/conversion step. The core area is 100 × 120 μm^2.
