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Aliasing Errors in Parallel Signature Analyzers
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作者 闵应骅 Yashwant K. Malaiya 金博平 《Journal of Computer Science & Technology》 SCIE EI CSCD 1990年第1期24-40,共17页
A Linear Feedback Shift Register (LFSR)can be used to compress test response data as a Signature Analyzer(SA). Parallel Signature Analyzers (PSAs) implemented as multiple input LFSRs are faster and re- quire less hard... A Linear Feedback Shift Register (LFSR)can be used to compress test response data as a Signature Analyzer(SA). Parallel Signature Analyzers (PSAs) implemented as multiple input LFSRs are faster and re- quire less hardware overhead than Serial Signature Analyzers (SSAs)for compacting test response data for Built-In Serf-Test (BIST)in IC or hoard-testing environments. However, the SAs are prone to aliasing errors because of some specific types of error patterns. An alias is a faulty output signature that is identical to the fault-free signature. A penetrating analysis of detecting capability of SAs depends strongly on mathematical manipulations, instead of being aware of some special cases or examples. In addition , the analysis should not be restricted to a particular structure of LFSR, but be appropriate for various structures of LFSRs. This pa- per presents necessary and sufficient conditions for aliasing errors based on a complete mathematical descrip- tion of various types of SAs. An LFSR reconfiguration scheme is suggested which will prevent any aliasing double errors. Such a prevention cannot be obtained by any extension of an LFSR. 展开更多
关键词 Aliasing Errors in Parallel Signature Analyzers MF XOR
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