Effect of triangle structure defects in a 180-μm-thick as-grown n-type 4H-SiC homoepitaxial layer on the carrier lifetime is quantitatively analyzed, which is grown by a horizontal hot-wall chemical vapor deposition ...Effect of triangle structure defects in a 180-μm-thick as-grown n-type 4H-SiC homoepitaxial layer on the carrier lifetime is quantitatively analyzed, which is grown by a horizontal hot-wall chemical vapor deposition reactor.By microwave photoconductivity decay lifetime measurements and photoluminescence measurements, the results show that the average carrier lifetime of as-grown epilayer across the whole wafer is 2.59μs, while it is no more than 1.34μs near a triangle defect（TD）. The scanning transmission electron microscope results show that the triangle structure defects have originated from 3C-SiC polytype and various types of as-grown stacking faults.Compared with the as-grown stacking faults, the 3C-SiC polytype has a great impact on the lifetime. The reduction of TD is essential to increasing the carrier lifetime of the as-grown thick epilayer.展开更多
The effect of nitric oxide（NO） annealing on charge traps in the oxide insulator and transition layer in n-type4H–Si C metal–oxide–semiconductor（MOS） devices has been investigated using the time-dependent bias s...The effect of nitric oxide（NO） annealing on charge traps in the oxide insulator and transition layer in n-type4H–Si C metal–oxide–semiconductor（MOS） devices has been investigated using the time-dependent bias stress（TDBS）,capacitance–voltage（C–V）,and secondary ion mass spectroscopy（SIMS）.It is revealed that two main categories of charge traps,near interface oxide traps（Nniot） and oxide traps（Not）,have different responses to the TDBS and C–V characteristics in NO-annealed and Ar-annealed samples.The Nniotare mainly responsible for the hysteresis occurring in the bidirectional C–V characteristics,which are very close to the semiconductor interface and can readily exchange charges with the inner semiconductor.However,Not is mainly responsible for the TDBS induced C–V shifts.Electrons tunneling into the Not are hardly released quickly when suffering TDBS,resulting in the problem of the threshold voltage stability.Compared with the Ar-annealed sample,Nniotcan be significantly suppressed by the NO annealing,but there is little improvement of Not.SIMS results demonstrate that the Nniotare distributed within the transition layer,which correlated with the existence of the excess silicon.During the NO annealing process,the excess Si atoms incorporate into nitrogen in the transition layer,allowing better relaxation of the interface strain and effectively reducing the width of the transition layer and the density of Nniot.展开更多
基金Supported by the National Key Research and Development Program of China under Grant No 2016YFB0400500
文摘Effect of triangle structure defects in a 180-μm-thick as-grown n-type 4H-SiC homoepitaxial layer on the carrier lifetime is quantitatively analyzed, which is grown by a horizontal hot-wall chemical vapor deposition reactor.By microwave photoconductivity decay lifetime measurements and photoluminescence measurements, the results show that the average carrier lifetime of as-grown epilayer across the whole wafer is 2.59μs, while it is no more than 1.34μs near a triangle defect（TD）. The scanning transmission electron microscope results show that the triangle structure defects have originated from 3C-SiC polytype and various types of as-grown stacking faults.Compared with the as-grown stacking faults, the 3C-SiC polytype has a great impact on the lifetime. The reduction of TD is essential to increasing the carrier lifetime of the as-grown thick epilayer.
基金Project supported by the National Natural Science Foundation of China(Grant Nos.61404098 and 61274079)the Doctoral Fund of Ministry of Education of China(Grant No.20130203120017)+2 种基金the National Key Basic Research Program of China(Grant No.2015CB759600)the National Grid Science&Technology Project,China(Grant No.SGRI-WD-71-14-018)the Key Specific Project in the National Science&Technology Program,China(Grant Nos.2013ZX02305002-002 and 2015CB759600)
文摘The effect of nitric oxide（NO） annealing on charge traps in the oxide insulator and transition layer in n-type4H–Si C metal–oxide–semiconductor（MOS） devices has been investigated using the time-dependent bias stress（TDBS）,capacitance–voltage（C–V）,and secondary ion mass spectroscopy（SIMS）.It is revealed that two main categories of charge traps,near interface oxide traps（Nniot） and oxide traps（Not）,have different responses to the TDBS and C–V characteristics in NO-annealed and Ar-annealed samples.The Nniotare mainly responsible for the hysteresis occurring in the bidirectional C–V characteristics,which are very close to the semiconductor interface and can readily exchange charges with the inner semiconductor.However,Not is mainly responsible for the TDBS induced C–V shifts.Electrons tunneling into the Not are hardly released quickly when suffering TDBS,resulting in the problem of the threshold voltage stability.Compared with the Ar-annealed sample,Nniotcan be significantly suppressed by the NO annealing,but there is little improvement of Not.SIMS results demonstrate that the Nniotare distributed within the transition layer,which correlated with the existence of the excess silicon.During the NO annealing process,the excess Si atoms incorporate into nitrogen in the transition layer,allowing better relaxation of the interface strain and effectively reducing the width of the transition layer and the density of Nniot.
