对模数转换器中的传统开关电路的导通电阻进行了详细的理论分析,提出了一种互补型栅压自举开关电路。该电路结构相比于传统开关,通过少量的功耗代价换取了更优的频域性能,在不同工艺角下具有更好的鲁棒性,适用于先进工艺下的低电压工作...对模数转换器中的传统开关电路的导通电阻进行了详细的理论分析,提出了一种互补型栅压自举开关电路。该电路结构相比于传统开关,通过少量的功耗代价换取了更优的频域性能,在不同工艺角下具有更好的鲁棒性,适用于先进工艺下的低电压工作环境。互补型栅压自举开关电路采用28 nm工艺设计,在1 V的电源电压下,对800 f F的负载电容进行速率为800 MS/s的采样,在低频输入下(181.25 MHz)实现的无杂散动态范围(SFDR)为89 d B,四倍奈奎斯特输入频率下(1 556 MHz)实现的SFDR为65 d B,开关电路面积为80μm×20μm。展开更多
This paper presents a high-speed high-resolution pipelined ADC with low power and small area. The proposed ADC is designed based on the analysis of the stage scaling theory and the residual amplifiers are shared by tw...This paper presents a high-speed high-resolution pipelined ADC with low power and small area. The proposed ADC is designed based on the analysis of the stage scaling theory and the residual amplifiers are shared by two cascading MDACs to reduce power consumption. Shared op-amps with two split input paths are presented in this paper to eliminate the nonlinearity effects such as memory effect and crosstalk. Dynamic pre-amplified comparators are employed to decrease the static power consumption and suppress the kick-back in the comparators. This ADC is implemented in SMIC 0.18/zm CMOS process with an area of 3.1 mm2. With a sampling rate of 100 MS/s, spurious-free dynamic range （SFDR） and signal-to-noise plus distortion ratio （SNDR） of the ADC are 82.7 dB and 69.1 dB, respectively. For signals up to 100 MHz, the SFDR and SNDR achieve 81.4 dB and 65.8 dB. The power consumption is 121 mW with a 1.8 V supply voltage.展开更多
文摘对模数转换器中的传统开关电路的导通电阻进行了详细的理论分析,提出了一种互补型栅压自举开关电路。该电路结构相比于传统开关,通过少量的功耗代价换取了更优的频域性能,在不同工艺角下具有更好的鲁棒性,适用于先进工艺下的低电压工作环境。互补型栅压自举开关电路采用28 nm工艺设计,在1 V的电源电压下,对800 f F的负载电容进行速率为800 MS/s的采样,在低频输入下(181.25 MHz)实现的无杂散动态范围(SFDR)为89 d B,四倍奈奎斯特输入频率下(1 556 MHz)实现的SFDR为65 d B,开关电路面积为80μm×20μm。
基金Project supported by the National Key Technology R&D Program(No.2012BAI13B07)
文摘This paper presents a high-speed high-resolution pipelined ADC with low power and small area. The proposed ADC is designed based on the analysis of the stage scaling theory and the residual amplifiers are shared by two cascading MDACs to reduce power consumption. Shared op-amps with two split input paths are presented in this paper to eliminate the nonlinearity effects such as memory effect and crosstalk. Dynamic pre-amplified comparators are employed to decrease the static power consumption and suppress the kick-back in the comparators. This ADC is implemented in SMIC 0.18/zm CMOS process with an area of 3.1 mm2. With a sampling rate of 100 MS/s, spurious-free dynamic range （SFDR） and signal-to-noise plus distortion ratio （SNDR） of the ADC are 82.7 dB and 69.1 dB, respectively. For signals up to 100 MHz, the SFDR and SNDR achieve 81.4 dB and 65.8 dB. The power consumption is 121 mW with a 1.8 V supply voltage.
