A differential LC voltage controlled oscillator (VCO) employing parasitic vertical-NPN (V-NPN) transistors as a negative gm-cell is presented to improve the close-in phase noise. The V-NPN transistors have lower flick...A differential LC voltage controlled oscillator (VCO) employing parasitic vertical-NPN (V-NPN) transistors as a negative gm-cell is presented to improve the close-in phase noise. The V-NPN transistors have lower flicker noise compared to MOS transistors. DC and AC characteristics of the V-NPN transistors are measured to facilitate the VCO design. The proposed VCO is implemented in a 0.18 μm CMOS RF/mixed signal process, and the measurement results show the close-in phase noise is improved by 3.5-9.1 dB from 100 Hz to 10 kHz offset compared to that of a similar CMOS VCO. The proposed VCO consumes only 0.41 mA from a 1.5 V power supply.展开更多
This paper presents a fully differential dual gain low noise amplifier(DGLNA) for low power 2.45-GHz ZigBee/IEEE 802.15.4 applications.The effect of input parasitics on the inductively degenerated cascode LNA is analy...This paper presents a fully differential dual gain low noise amplifier(DGLNA) for low power 2.45-GHz ZigBee/IEEE 802.15.4 applications.The effect of input parasitics on the inductively degenerated cascode LNA is analyzed.Circuit design details within the guidelines of the analysis are presented.The chip was implemented in SMIC 0.18-μm 1P6M RF/mixed signal CMOS process.The DGLNA achieves a maximum gain of 8 dB and a minimum gain of 1 dB with good input return loss.In high gain mode, the measured noise figure(NF) is 2.3-3 dB in the whole 2.45-GHz ISM band.The measured 1-dB compression point, IIP3 and IIP2 is-9, 1 and 33 dBm, respectively.The DGLNA consumes 2 mA of current from a 1.8 V power supply.展开更多
An ultra-low-power CMOS temperature sensor with analog-to-digital readout circuitry for RFID appli- cations was implemented in a 0.18-μm CMOS process. To achieve ultra-low power consumption, an error model is propose...An ultra-low-power CMOS temperature sensor with analog-to-digital readout circuitry for RFID appli- cations was implemented in a 0.18-μm CMOS process. To achieve ultra-low power consumption, an error model is proposed and the corresponding novel temperature sensor front-end with a new double-measure method is presented. Analog-to-digital conversion is accomplished by a sigma-delta converter. The complete system consumes only 26 μA @ 1.8 V for continuous operation and achieves an accuracy of ±0.65 °C from –20 to 120 °C after calibration at one temperature.展开更多
基金supported by the Innovation Founding of Fudan University,China
文摘A differential LC voltage controlled oscillator (VCO) employing parasitic vertical-NPN (V-NPN) transistors as a negative gm-cell is presented to improve the close-in phase noise. The V-NPN transistors have lower flicker noise compared to MOS transistors. DC and AC characteristics of the V-NPN transistors are measured to facilitate the VCO design. The proposed VCO is implemented in a 0.18 μm CMOS RF/mixed signal process, and the measurement results show the close-in phase noise is improved by 3.5-9.1 dB from 100 Hz to 10 kHz offset compared to that of a similar CMOS VCO. The proposed VCO consumes only 0.41 mA from a 1.5 V power supply.
基金supported by the Innovation Fund of Fudan University,Shanghai, China
文摘This paper presents a fully differential dual gain low noise amplifier(DGLNA) for low power 2.45-GHz ZigBee/IEEE 802.15.4 applications.The effect of input parasitics on the inductively degenerated cascode LNA is analyzed.Circuit design details within the guidelines of the analysis are presented.The chip was implemented in SMIC 0.18-μm 1P6M RF/mixed signal CMOS process.The DGLNA achieves a maximum gain of 8 dB and a minimum gain of 1 dB with good input return loss.In high gain mode, the measured noise figure(NF) is 2.3-3 dB in the whole 2.45-GHz ISM band.The measured 1-dB compression point, IIP3 and IIP2 is-9, 1 and 33 dBm, respectively.The DGLNA consumes 2 mA of current from a 1.8 V power supply.
文摘An ultra-low-power CMOS temperature sensor with analog-to-digital readout circuitry for RFID appli- cations was implemented in a 0.18-μm CMOS process. To achieve ultra-low power consumption, an error model is proposed and the corresponding novel temperature sensor front-end with a new double-measure method is presented. Analog-to-digital conversion is accomplished by a sigma-delta converter. The complete system consumes only 26 μA @ 1.8 V for continuous operation and achieves an accuracy of ±0.65 °C from –20 to 120 °C after calibration at one temperature.
