A low-voltage-driven digital-droplet-transporting chip with an open structure is designed,fabricated and characterized.The digital microfluidic chip is fabricated by the silicon planar process.Using only a single elec...A low-voltage-driven digital-droplet-transporting chip with an open structure is designed,fabricated and characterized.The digital microfluidic chip is fabricated by the silicon planar process.Using only a single electrode panel,the droplet on the chip can be manipulated by electrostatic force under a dc driving voltage.The actuation principle is proposed and verified by the experiment.The experimental results show that the minimum driving voltage decreases as the thickness of the dielectric layer decreases.The driving voltage for a 3µL deionized(DI)water droplet is reduced to 15 V in air and 13.5 V in oil by employing a thin dielectric layer of 600 nm with a high dielectric constant and a coating hydrophobic layer on the top.The DI water droplets are also demonstrated to be transported in two dimensions smoothly in a programmable manner,and the maximum transport speed reaches 96 mm/s.The droplets of normal saline,a solution of 0.9 wt%NaCl,are also successfully manipulated on the chip.展开更多
Nanoscale refinement on a （100） oriented silicon-on-insulator （SOI） wafer was introduced by using tetra-methyl-ammonium hydroxide （TMAH, 25 wt%） anisotropic silicon etchant, with temperature kept at 50 ℃ to ach...Nanoscale refinement on a （100） oriented silicon-on-insulator （SOI） wafer was introduced by using tetra-methyl-ammonium hydroxide （TMAH, 25 wt%） anisotropic silicon etchant, with temperature kept at 50 ℃ to achieve precise etching of the （111） crystal plane. Specifically for a silicon nanowire （SiNW） with oxide sidewall protection, the in situ TMAH process enabled effective size reduction in both lateral （2.3 nm/min） and vertical （1.7 nm/min） dimensions. A sub-50 nm SiNW with a length of microns with uniform triangular cross-section was achieved accordingly, yielding enhanced field effect transistor （FET） characteristics in comparison with its 100 nm- wide pre-refining counterpart, which demonstrated the feasibility of this highly controllable refinement process. Detailed examination revealed that the high surface quality of the （111） plane, as well as the bulk depletion property should be the causes of this electrical enhancement, which implies the great potential of the as-made cost-effective SiNW FET device in many fields.展开更多
基金by the National Basic Research Program of China under Grant No 2011CB309501the Fund for Creative Research of NSFC under Grant No 61021064+1 种基金the Key Project of NSFC under Grant No 60936001the National Natural Science Foundation of China under Grant No 60876037.
文摘A low-voltage-driven digital-droplet-transporting chip with an open structure is designed,fabricated and characterized.The digital microfluidic chip is fabricated by the silicon planar process.Using only a single electrode panel,the droplet on the chip can be manipulated by electrostatic force under a dc driving voltage.The actuation principle is proposed and verified by the experiment.The experimental results show that the minimum driving voltage decreases as the thickness of the dielectric layer decreases.The driving voltage for a 3µL deionized(DI)water droplet is reduced to 15 V in air and 13.5 V in oil by employing a thin dielectric layer of 600 nm with a high dielectric constant and a coating hydrophobic layer on the top.The DI water droplets are also demonstrated to be transported in two dimensions smoothly in a programmable manner,and the maximum transport speed reaches 96 mm/s.The droplets of normal saline,a solution of 0.9 wt%NaCl,are also successfully manipulated on the chip.
基金Project supported by the State Key Development Program for Basic Research of China(No.2006CB300403)the National Hi-Tech Research and Development Program of China(No.2007AA03Z308)the Fund for Creative Research of the National Natural Science Foundation of China(No.60721004)
文摘Nanoscale refinement on a （100） oriented silicon-on-insulator （SOI） wafer was introduced by using tetra-methyl-ammonium hydroxide （TMAH, 25 wt%） anisotropic silicon etchant, with temperature kept at 50 ℃ to achieve precise etching of the （111） crystal plane. Specifically for a silicon nanowire （SiNW） with oxide sidewall protection, the in situ TMAH process enabled effective size reduction in both lateral （2.3 nm/min） and vertical （1.7 nm/min） dimensions. A sub-50 nm SiNW with a length of microns with uniform triangular cross-section was achieved accordingly, yielding enhanced field effect transistor （FET） characteristics in comparison with its 100 nm- wide pre-refining counterpart, which demonstrated the feasibility of this highly controllable refinement process. Detailed examination revealed that the high surface quality of the （111） plane, as well as the bulk depletion property should be the causes of this electrical enhancement, which implies the great potential of the as-made cost-effective SiNW FET device in many fields.
