This paper presents the design and implementation of a low power digital signal processor(THUCID-SP-1)targeting at application for cochlear implants.Multi-level low power strategies including algorithmoptimization,ope...This paper presents the design and implementation of a low power digital signal processor(THUCID-SP-1)targeting at application for cochlear implants.Multi-level low power strategies including algorithmoptimization,operand isolation,clock gating and memory partitioning are adopted in the processor designto reduce the power consumption.Experimental results show that the complexity of the Continuous Inter-leaved Sampling(CIS)algorithm is reduced by more than 80% and the power dissipation of the hardwarealone is reduced by about 25% with the low power methods.The THUCIDSP-l prototype,fabricated in0.18-μm standard CMOS process,consumes only 1.91 mW when executing the CIS algorithm at 3 MHz.展开更多
基金Supported by the National Natural Science Foundation of China (No. 60475018)
文摘This paper presents the design and implementation of a low power digital signal processor(THUCID-SP-1)targeting at application for cochlear implants.Multi-level low power strategies including algorithmoptimization,operand isolation,clock gating and memory partitioning are adopted in the processor designto reduce the power consumption.Experimental results show that the complexity of the Continuous Inter-leaved Sampling(CIS)algorithm is reduced by more than 80% and the power dissipation of the hardwarealone is reduced by about 25% with the low power methods.The THUCIDSP-l prototype,fabricated in0.18-μm standard CMOS process,consumes only 1.91 mW when executing the CIS algorithm at 3 MHz.
