A low power and low phase noise phase-locked loop（PLL） design for low voltage（0.8 V） applications is presented.The voltage controlled oscillator（VCO） operates from a 0.5 V voltage supply,while the other blocks o...A low power and low phase noise phase-locked loop（PLL） design for low voltage（0.8 V） applications is presented.The voltage controlled oscillator（VCO） operates from a 0.5 V voltage supply,while the other blocks operate from a 0.8 V supply.A differential NMOS-only topology is adopted for the oscillator,a modified precharge topology is applied in the phase-frequency detector（PFD）,and a new feedback structure is utilized in the charge pump（CP） for ultra-low voltage applications.The divider adopts the extended true single phase clock DFF in order to operate in the high frequency region and save circuit area and power.In addition,several novel design techniques,such as removing the tail current source,are demonstrated to cut down the phase noise.Implemented in the SMIC 0.13μm RF CMOS process and operated at 0.8 V supply voltage,the PLL measures a phase noise of-112.4 dBc/Hz at an offset frequency of 1 MHz from the carrier and a frequency range of 3.166-3.383 GHz.The improved PFD and the novel CP dissipate 0.39 mW power from a 0.8 V supply.The occupied chip area of the PFD and CP is 100×100μm^2.The chip occupies 0.63 mm^2,and draws less than 6.54 mW from a 0.8 V supply.展开更多
文摘A low power and low phase noise phase-locked loop（PLL） design for low voltage（0.8 V） applications is presented.The voltage controlled oscillator（VCO） operates from a 0.5 V voltage supply,while the other blocks operate from a 0.8 V supply.A differential NMOS-only topology is adopted for the oscillator,a modified precharge topology is applied in the phase-frequency detector（PFD）,and a new feedback structure is utilized in the charge pump（CP） for ultra-low voltage applications.The divider adopts the extended true single phase clock DFF in order to operate in the high frequency region and save circuit area and power.In addition,several novel design techniques,such as removing the tail current source,are demonstrated to cut down the phase noise.Implemented in the SMIC 0.13μm RF CMOS process and operated at 0.8 V supply voltage,the PLL measures a phase noise of-112.4 dBc/Hz at an offset frequency of 1 MHz from the carrier and a frequency range of 3.166-3.383 GHz.The improved PFD and the novel CP dissipate 0.39 mW power from a 0.8 V supply.The occupied chip area of the PFD and CP is 100×100μm^2.The chip occupies 0.63 mm^2,and draws less than 6.54 mW from a 0.8 V supply.
