“Ni-Zn铁氧体颗粒-光刻胶”覆盖的片上射频电感

本文报道了采用新型“纳米颗粒-光刻胶”混合旋涂技术制作的片上射频Ni-Zn铁氧体磁膜微电感。成相良好的Ni0.3Zn0.6Cu0.1Fe2O4铁氧体纳米颗粒在光刻胶中均匀混合,再将该混合物涂覆在螺旋电感线圈上,实现电感性能的提升。这种新型低温工艺避免了常规制作铁氧体器件方法带来的高温处理（〉600°C）对集成电路的破坏。与无磁膜覆盖样品对比,铁氧体覆盖电感的电感量在0.1～4GHz提升了14～27%。这是实现高性能、全兼容铁氧体集成片上RFIC电感的一种很有前景的途径。

Enhanced Offset Averaging Technique for Flash ADC Design

This paper presents a new combined AC/DC-coupled output averaging technique for input amplifier design of flash analog-to-digital converters （ADC）. The new offset averaging design technique takes full advantage of traditional DC-coupled resistance averaging and AC-coupled capacitance averaging techniques to minimize offset-induced ADC nonlinearities. Circuit analysis allows selection of optimum resistance and capacitance averaging factors to achieve maximum offset reduction in ADC designs. The new averaging method is verified in designing a 4 bit 1 Gs/s flash ADC that is implemented in foundry 0.13 μm CMOS technology.

Whole-Chip ESD Protection Design for RF and AMS ICs

As integrated circuits （IC） technologies advance into very-deep-sub-micron （VDSM）, electrostatic discharge （ESD） failure becomes one of the most devastating IC reliability problems and on-chip ESD protection design emerges as a major challenge to radio frequency （RF）, analog, and mixed-signal （AMS） IC designs. This paper reviews key design aspects and recent advances in whole-chip ESD protection designs for RF/AMS IC applications in CMOS technologies.

ESD-Induced Noise to Low Noise Amplifier Circuits in BiCMOS

Electrostatic discharge （ESD） induced parasitic effects have serious impacts on performance of radio frequency （RF） integrated circuits （IC）. This paper discusses a comprehensive noise analysis procedure for ESD protection structures and their negative influences on RF ICs. Noise figures （NFs） of commonly used ESD protection structures and their impacts on a single-chip 5.5 GHz low-noise amplifier （LNA） circuit were depicted. A design example in 0.18 μm SiGe BiCMOS was presented. Measurement results confirm that significant noise degradation occurs in the LNA circuit due to ESD-induced noise effects. A practical design procedure for ESD-protected RF ICs is provided for real-world RF IC optimization.

Design of Magnetic RF Inductor in CMOS

Traditional planar inductors in Radio Frequency （RF） Integrated Circuits （ICs） are plagued by large areas, low quality, and low frequencies. This paper describes a magnetic-based CMOS-compatible RF in- ductor. Magnetic-core inductors with various ferrite-filled structures, spiral structures, and magnetic material permeabilities were simulated to show that this inductor greatly improves the inductance by up to 97% and quality factor by 18.6% over a multi-GHz frequency range. The results indicate that the inductor is a very promising and viable solution to realize miniature, high quality, and high frequency on-chip inductors for high-end RF ICs.

A TAILWIND FOR ENTREPRENEURS

Beijing Review： As we can see, industrial leaders already exist in many Internetrelated segments. Which areas, from your point of view, will create new leaders, and therefore, should investors pay the most attention to？ What kinds of business start-ups are you most interested in？

机器的大脑

一场突发悲剧敲响了警钟:2011年日本大地震和海啸引发福岛第一核电站核事故,给众多机器人专家敲响了警钟。这场事故发生后,媒体报道高剂量辐射阻碍了工人实施紧急措施,例如操作压力阀。其实这是一项非常合适机器人的任务,但无论是日本还是其他国家的机器人都没有能力关闭这个阀门。福岛核事故使机器人界意识到:技术需要走出实验室,进入现实世界。