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FPGA Implementation of a Scalable and Highly Parallel Architecture for Restricted Boltzmann Machines
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作者 Kodai Ueyoshi Takao Marukame +2 位作者 Tetsuya Asai Masato Motomura alexandre schmid 《Circuits and Systems》 2016年第9期2132-2141,共10页
Restricted Boltzmann Machines (RBMs) are an effective model for machine learning;however, they require a significant amount of processing time. In this study, we propose a highly parallel, highly flexible architecture... Restricted Boltzmann Machines (RBMs) are an effective model for machine learning;however, they require a significant amount of processing time. In this study, we propose a highly parallel, highly flexible architecture that combines small and completely parallel RBMs. This proposal addresses problems associated with calculation speed and exponential increases in circuit scale. We show that this architecture can optionally respond to the trade-offs between these two problems. Furthermore, our FPGA implementation performs at a 134 times processing speed up factor with respect to a conventional CPU. 展开更多
关键词 Deep Learning Restricted Boltzmann Machines (RBMs) FPGA ACCELERATION
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