Optimal distribution feeder reconfiguration （DFR） is a valuable and costless approach to increase the load balance, reduce the amount of power losses, and improve the voltage of the buses. In this way, this paper ai...Optimal distribution feeder reconfiguration （DFR） is a valuable and costless approach to increase the load balance, reduce the amount of power losses, and improve the voltage of the buses. In this way, this paper aims to investigate the optimal DFR strategy as a proper tool to improve the reliability of the radial distribution networks. The idea of failure rate reduction is employed to see the effect of feeder current reduction on the reliability of the system more accurately. The objects to be investigated are system average interruption frequency index （SAIFI）, system average interruption duration index （SAIDI）, average energy not supplied （AENS） and total active power losses. The problem is then formulated in a stochastic framework based on the point estimate method （PEM） to handle the uncertainty effects. The feasibility and satisfying performance of the proposed method is examined on a standard IEEE test system.展开更多
In recent studies, reversible logic has emerged as a great scene of research, having applications in low power CMOS circuits, optical computing, quantum computing and nanotechnology. The classical logic gates such as ...In recent studies, reversible logic has emerged as a great scene of research, having applications in low power CMOS circuits, optical computing, quantum computing and nanotechnology. The classical logic gates such as AND, OR, EXOR and EXNOR are not reversible. In the existing literature, reversible sequential circuits designs are offered that are improved for the number of the garbage outputs and reversible gates. Minimizing the number of garbage is very noticeable. In the present paper, we show a design of the reversible comparator based on the quantum gates implementation of the reversible DG gate. The reversible DG gate is designed by using 3 × 3 quantum gates such as NOT, CNOT, Controlled-V and Controlled-V+ gates. Also, we have used the TR gate and various types of quantum gates in the implementation results. Low power three-bit comparator is designed using DG Gate, New Gate and Fredkin Gate. In order to evaluate the benefit of using the DG gate proposed in this paper, one-bit comparator is constructed. The design is useful for the future computing techniques like quantum computers. The proposed designs are implemented using VHDL and functionally investigated using Quartus II simulator.展开更多
文摘Optimal distribution feeder reconfiguration （DFR） is a valuable and costless approach to increase the load balance, reduce the amount of power losses, and improve the voltage of the buses. In this way, this paper aims to investigate the optimal DFR strategy as a proper tool to improve the reliability of the radial distribution networks. The idea of failure rate reduction is employed to see the effect of feeder current reduction on the reliability of the system more accurately. The objects to be investigated are system average interruption frequency index （SAIFI）, system average interruption duration index （SAIDI）, average energy not supplied （AENS） and total active power losses. The problem is then formulated in a stochastic framework based on the point estimate method （PEM） to handle the uncertainty effects. The feasibility and satisfying performance of the proposed method is examined on a standard IEEE test system.
文摘In recent studies, reversible logic has emerged as a great scene of research, having applications in low power CMOS circuits, optical computing, quantum computing and nanotechnology. The classical logic gates such as AND, OR, EXOR and EXNOR are not reversible. In the existing literature, reversible sequential circuits designs are offered that are improved for the number of the garbage outputs and reversible gates. Minimizing the number of garbage is very noticeable. In the present paper, we show a design of the reversible comparator based on the quantum gates implementation of the reversible DG gate. The reversible DG gate is designed by using 3 × 3 quantum gates such as NOT, CNOT, Controlled-V and Controlled-V+ gates. Also, we have used the TR gate and various types of quantum gates in the implementation results. Low power three-bit comparator is designed using DG Gate, New Gate and Fredkin Gate. In order to evaluate the benefit of using the DG gate proposed in this paper, one-bit comparator is constructed. The design is useful for the future computing techniques like quantum computers. The proposed designs are implemented using VHDL and functionally investigated using Quartus II simulator.
