Performance projections for ballistic carbon nanotube FinFET at circuit level

A novel three-dimensional device structure for a carbon nanotube （CNT） fin field-effect transistor （FinFET） is proposed and evaluated. We evaluated the potential of the CNT FinFET compared with a Si FinFET at a 22-nm node at the circuit level using three performance metrics including propagation delay, total power dissipation, and energy-delay product （EDP）. Compared with a Si FinFET, the CNT FinFET presents obvious advantages in speed and EDP arising from its almost much larger current density but also results in a higher total power dissipation, especially at a low threshold voltage （V~ = 1/3Vaa）. A suitable improvement in Vth can effectively contribute to a significant suppression of leakage current and power dissipation, and then an obvious optimization is obtained in the EDP with an acceptable sacrifice in speed. In particular, CNT FinFETs with optimized threshold voltages can provide an EDP advantage of approximately 50 times over Si FinFETs under a low supply voltage （Vdd -- 0.4 V）, suggesting great potential for CNT FinFET-based integrated circuits.

Suppression of leakage current in carbon nanotube field-effect transistors

Carbon nanotube field-effect transistor(CNT FET)has been considered as a promising candidate for future high-performance and low-power integrated circuits(ICs)applications owing to its ballistic transport and excellent immunity to short channel effects(SCEs).Still,it easily suffers from the ambipolar property,and severe leakage current at off-state originated from gate-induced drain leakage(GIDL)in CNT FETs with small bandgap.Although some modifications on device structure have been experimentally demonstrated to suppress the leakage current in CNT FETs,there is still a lack of the structure with excellent scalability,which will hamper the development of CNT FETs toward a competitive technology node.Here,we explore how the device geometry design affects the leakage current in CNT FETs,and then propose the possible device structures to suppress off-state current and check their availability through the two-dimensional(2D)TCAD simulations.Among all the proposed structures,the L-shaped-spacer CNT FET exhibits significantly suppressed leakage current and excellent scalability down to sub-50 nm with a simple self-aligned gate process.According to the simulation results,the 50 nm gate-length L-shaped-spacer CNT FET exhibits an off-state current as low as approximately 1 nA/μm and an on-current as high as about 2.1 mA/μm at a supply voltage of-1 V and then can be extended as a universal device structure to suppress leakage current for all the narrow-bandgap semiconductors based FETs.

Field-effect at electrical contacts to two-dimensional materials

The inferior electrical contact to two-dimensional(2D)materials is a critical challenge for their application in post-silicon very large-scale integrated circuits.Electrical contacts were generally related to their resistive effect,quantified as contact resistance.With a systematic investigation,this work demonstrates a capacitive metal-insulator-semiconductor(MIS)field-effect at the electrical contacts to 2D materials:The field-effect depletes or accumulates charge carriers,redistributes the voltage potential,and gives rise to abnormal current saturation and nonlinearity.On one hand,the current saturation hinders the devices’driving ability,which can be eliminated with carefully engineered contact configurations.On the other hand,by introducing the nonlinearity to monolithic analog artificial neural network circuits,the circuits’perception ability can be significantly enhanced,as evidenced using a coronavirus disease 2019(COVID-19)critical illness prediction model.This work provides a comprehension of the field-effect at the electrical contacts to 2D materials,which is fundamental to the design,simulation,and fabrication of electronics based on 2D materials.