Offset-free DC-coupled analog frontend circuit for high-dynamicrange signals

The analog frontend(AFE)coupling circuit is a crucial processing element for data acquisition systems based on analog-to-digital converters(ADCs).Currently,high-speed and high-resolution ADCs are predominantly designed with differential input stages.Conventional highspeed ADC drivers are mainly AC-coupled by employing transformers(Baluns)or fully differential amplifiers(FDAs)with blocking capacitors.However,the results of this study indicate that a certain degree of DC offset error exists and manifests itself as the baseline error in the presence of power dividers connecting several DC-coupled channels that implement high-dynamic-range(HDR)signal conditioning.The study involves a theoretical analysis and explanation of the baseline offset error.The offset error can potentially lead to unexpected out-of-range issues for sampling devices,including high-speed ADCs and switched capacitor array ASICs.High-performance FDAs are adopted,and an offset-free DC-coupled AFE circuit is proposed to address the aforementioned issue using twostage amplification and a resistive attenuator.The proposed methodology is verified via circuit simulations and hardware design.Thus,the baseline offset problem can be accurately solved using the proposed circuit by minimizing the neglectable error.The proposed circuit facilitates improvements in the high-precision measurement of HDR signals in many nuclear physics experiments and some applications in the DC-coupling scheme with FDAs involving resistive power dividers.

Design and offline processing of an ultrafast digitizer based on internal cascaded DRS4

In this paper, we present an ultrafast digitizer utilizing the DRS4 switched capacitor array applicationspecific integrated circuit to achieve an ultrafast sampling speed of at most 5 GS/s. We cascaded all eight channels(sub-channels) of a single DRS4 chip for increased storage depth. The digitizer contains four DRS4 chips, a quadchannel analog-to-digital converter,a controlling fieldprogrammable gate array, a PXI interface, and an SFP+connector. Consequently, each DRS4 channel has a depth of 8192 points and a vertical resolution of 14 bits. The readout sequences should be broken into several segments and then reordered to obtain the correct sequential data sets, and this offline procedure varies in different readout modes. This paper describes the design and implementation of the hardware;in particular, the respective processing procedures are described in detail. Furthermore, the offset error is calibrated and corrected to improve the precision of the captured waveform in both single-channel and highresolution modes.