Contact optimisation strategy for wafer-scale field-effect transistors based on two-dimensional semiconductors

Two-dimensional(2D)semiconductors can be utilized to continually miniaturize nanoscale electronic de-vices.However,achieving a practical solution for satisfying electrical contact with 2D semiconductors remains challenging.In this study,we developed a novel contact structure with transferred multilayer(t-ML)MoS 2 by integrating both edge and top contact.After in-situ plasma treatment for the edge of the MoS 2 channel and successive metal deposition,we achieved 16 times lower contact resistivity(22.8 kΩμm)than that of the top contacted devices.The thickness-dependent electrical measurement indicates that edge contact is highly effective with thick MoS 2 due to the alleviated current-crowding effect re-sulting from the small contact area.The temperature-dependent transport measurement further confirms the effective minimization of the influence from the Schottky barrier and tunnelling barrier.Finally,the simplified resistor network model and energy-band diagram were proposed to understand the carrier transport mechanism.Our work provides a practical strategy for achieving excellent electrical contact between bulk metals and 2D semiconductors,paving the way for future large-scale 2D electronic devices.

Top gate engineering of field-effect transistors based on wafer-scale two-dimensional semiconductors

The investigation of two-dimensional(2D)materials has advanced into practical device applications,such as cascaded logic stages.However,incompatible electrical properties and inappropriate logic levels remain enormous challenges.In this work,a doping-free strategy is investigated by top gated(TG)MoS_(2) field-effect transistors(FETs)using various metal gates(Au,Cu,Ag,and Al).These metals with different work functions provide a convenient tuning knob for controlling threshold voltage(V_(th))for MoS_(2) FETs.For instance,the Al electrode can create an extra electron doping(n-doping)behavior in the MoS_(2) TG-FETs due to a dipole effect at the gate-dielectric interface.In this work,by achieving matched electrical properties for the load transistor and the driver transistor in an inverter circuit,we successfully demonstrate wafer-scale MoS_(2) inverter arrays with an optimized inverter switching threshold voltage(V_(M))of 1.5 V and a DC voltage gain of 27 at a supply voltage(V_(DD))of 3 V.This work offers a novel scheme for the fabrication of fully integrated multistage logic circuits based on wafer-scale MoS_(2) film.

Stacking monolayers at will:A scalable device optimization strategy for two-dimensional semiconductors

In comparison to monolayer(1L),multilayer(ML)two-dimensional(2D)semiconducting transition metal dichalcogenides(TMDs)exhibit more application potential for electronic and optoelectronic devices due to their improved current carrying capability,higher mobility,and broader spectral response.However,the investigation of devices based on wafer-scale ML-TMDs is still restricted by the synthesis of uniform and high-quality ML films.In this work,we propose a strategy of stacking MoS_(2) monolayers via a vacuum transfer method,by which one could obtain wafer-scale high-quality MoS_(2) films with the desired number of layers at will.The optical characteristics of these stacked ML-MoS_(2) films(>2L)indicate a weak interlayer coupling.The stacked MLMoS_(2) phototransistors show improved optoelectrical performances and a broader spectral response(approximately 300-1,000 nm)than that of 1L-MoS_(2).Additionally,the dual-gate ML-MoS_(2) transistors enable enhanced electrostatic control over the stacked ML-MoS_(2) channel,and the 3L and 4L thicknesses exhibit the optimal device performances according to the turning point of the current on/off ratio and the subthreshold swing.