In today’s modern design technology,post-silicon validation is an expensive and composite task.The major challenge involved in this method is that it has limited observability and controllability of internal signals....In today’s modern design technology,post-silicon validation is an expensive and composite task.The major challenge involved in this method is that it has limited observability and controllability of internal signals.There will be an issue during execution how to address the useful set of signals and store it in the on-chip trace buffer.The existing approaches are restricted to particular debug set-up where all the components have equivalent prominence at all the time.Practically,the verification engineers will emphasis only on useful functional regions or components.Due to some constraints like clock gating,some of the regions can be ignored during execution.Likewise,some of these regions can be verified deeply and have minimum errors compared to other control regions.The proposed system focusses on random signals that identify more errors which are prone to signal selection technique with low area overhead.To enhance the observability,a machine learning technique is developed.Based on the training samples of smaller designs,a model is developed to find out the contiguous neighbours of each flip-flop.This can eliminate the obstacles of unknown signals.This system demonstrates using Opencores and ISCAS’89 benchmark circuits that result in easy and fast error detection compared to the state-of-theart of other methods.This is also verified using gate-level error models by cross-validation of each debug run.展开更多
文摘In today’s modern design technology,post-silicon validation is an expensive and composite task.The major challenge involved in this method is that it has limited observability and controllability of internal signals.There will be an issue during execution how to address the useful set of signals and store it in the on-chip trace buffer.The existing approaches are restricted to particular debug set-up where all the components have equivalent prominence at all the time.Practically,the verification engineers will emphasis only on useful functional regions or components.Due to some constraints like clock gating,some of the regions can be ignored during execution.Likewise,some of these regions can be verified deeply and have minimum errors compared to other control regions.The proposed system focusses on random signals that identify more errors which are prone to signal selection technique with low area overhead.To enhance the observability,a machine learning technique is developed.Based on the training samples of smaller designs,a model is developed to find out the contiguous neighbours of each flip-flop.This can eliminate the obstacles of unknown signals.This system demonstrates using Opencores and ISCAS’89 benchmark circuits that result in easy and fast error detection compared to the state-of-theart of other methods.This is also verified using gate-level error models by cross-validation of each debug run.
