In this investigation,all-optical Toggle flip-flop event-driven memory is explored with data rate of 16 Gbit/s.Single mode optical fiber model is used as a nonlinear medium to generate the output set and reset pulses ...In this investigation,all-optical Toggle flip-flop event-driven memory is explored with data rate of 16 Gbit/s.Single mode optical fiber model is used as a nonlinear medium to generate the output set and reset pulses of a Toggle flip-flop,and the model is based on the bidirectional optical transmission principle,considering the fundamental effects of cross phase modulation and self-phase modulation with change in polarization state.The performance of a flip-flop is evaluated using truth table conditions and performance parameters such as Q factor,which is obtained as 380.92 d B for Q and 272.9 d B for■,and rising and falling times of 7.304 ps and 5.79 ps,respectively are obtained,which makes flip-flop design fast as compared to earlier design techniques.展开更多
This study presents a simple methodology for implementation of all optical JK flip flop for future optical high speed networks.The scheme utilizes electronic model of JK flip flop for implementation of all optical JK ...This study presents a simple methodology for implementation of all optical JK flip flop for future optical high speed networks.The scheme utilizes electronic model of JK flip flop for implementation of all optical JK flip flop at the bit rate of 7 Gbit/s.Firstly,all-optical AND and NOR gates are implemented.Furthermore,with the combination of these basic gate structures,the optical model of JK flip flop is verified.This structure makes use of two optical AND gates and two optical NOR gates.This technique uses a semiconductor optical amplifier(SOA)as the nonlinear medium to produce considerable amount of cross gain and cross phase modulation to attain truth table conditions of optical JK flip flop.In this method,the number of gates is reduced as compared to earlier schemes.Rise time and fall time of 5.6 ps with contrast ratio more than 60 dB are achieved in this design.展开更多
基金supported by the Science and Engineering Research Board,New Delhi for Research Grant Vide Sanction No:File No.EMR/2017/004162 dated 01-11-18。
文摘In this investigation,all-optical Toggle flip-flop event-driven memory is explored with data rate of 16 Gbit/s.Single mode optical fiber model is used as a nonlinear medium to generate the output set and reset pulses of a Toggle flip-flop,and the model is based on the bidirectional optical transmission principle,considering the fundamental effects of cross phase modulation and self-phase modulation with change in polarization state.The performance of a flip-flop is evaluated using truth table conditions and performance parameters such as Q factor,which is obtained as 380.92 d B for Q and 272.9 d B for■,and rising and falling times of 7.304 ps and 5.79 ps,respectively are obtained,which makes flip-flop design fast as compared to earlier design techniques.
基金supported by the Science&Engineering Research Board,New Delhi,India vide Sanction(No.EMR/2017/004162)。
文摘This study presents a simple methodology for implementation of all optical JK flip flop for future optical high speed networks.The scheme utilizes electronic model of JK flip flop for implementation of all optical JK flip flop at the bit rate of 7 Gbit/s.Firstly,all-optical AND and NOR gates are implemented.Furthermore,with the combination of these basic gate structures,the optical model of JK flip flop is verified.This structure makes use of two optical AND gates and two optical NOR gates.This technique uses a semiconductor optical amplifier(SOA)as the nonlinear medium to produce considerable amount of cross gain and cross phase modulation to attain truth table conditions of optical JK flip flop.In this method,the number of gates is reduced as compared to earlier schemes.Rise time and fall time of 5.6 ps with contrast ratio more than 60 dB are achieved in this design.
