Sparse Adversarial Learning for FDIA Attack Sample Generation in Distributed Smart

False data injection attack(FDIA)is an attack that affects the stability of grid cyber-physical system(GCPS)by evading the detecting mechanism of bad data.Existing FDIA detection methods usually employ complex neural networkmodels to detect FDIA attacks.However,they overlook the fact that FDIA attack samples at public-private network edges are extremely sparse,making it difficult for neural network models to obtain sufficient samples to construct a robust detection model.To address this problem,this paper designs an efficient sample generative adversarial model of FDIA attack in public-private network edge,which can effectively bypass the detectionmodel to threaten the power grid system.A generative adversarial network(GAN)framework is first constructed by combining residual networks(ResNet)with fully connected networks(FCN).Then,a sparse adversarial learning model is built by integrating the time-aligned data and normal data,which is used to learn the distribution characteristics between normal data and attack data through iterative confrontation.Furthermore,we introduce a Gaussian hybrid distributionmatrix by aggregating the network structure of attack data characteristics and normal data characteristics,which can connect and calculate FDIA data with normal characteristics.Finally,efficient FDIA attack samples can be sequentially generated through interactive adversarial learning.Extensive simulation experiments are conducted with IEEE 14-bus and IEEE 118-bus system data,and the results demonstrate that the generated attack samples of the proposed model can present superior performance compared to state-of-the-art models in terms of attack strength,robustness,and covert capability.

Constructive Texture Steganography Based on Compression Mapping of Secret Messages

This paper proposes a new constructive texture synthesis steganographic scheme by compressing original secret messages.First,we divide the original message into multiple bit blocks,which are transferred to decimal values and compressed into small decimal values by recording their interval sign characters.Then,a candidate pattern is generated by combining the given source pattern and boundary extension algorithm.Furthermore,we segment the candidate pattern into multiple candidate patches and use affine transformation algorithm to locate secret positions on a blank canvas,which are used to hide the sign characters by mapping the candidate patches.Finally,we select the candidate patches with minimal mean square error to represent secret bits to generate stego image by image quilting.Extensive experiments demonstrate that compared with existing texture steganographic methods,our method has a better visual quality,higher embedding capacity and security performance,while maintaining strong anti-steganalysis capability.

Accurate Reliability Analysis Methods for Approximate Computing Circuits

In recent years,Approximate Computing Circuits(ACCs)have been widely used in applications with intrinsic tolerance to errors.With the increased availability of approximate computing circuit approaches,reliability analysis methods for assessing their fault vulnerability have become highly necessary.In this study,two accurate reliability evaluation methods for approximate computing circuits are proposed.The reliability of approximate computing circuits is calculated on the basis of the iterative Probabilistic Transfer Matrix(PTM)model.During the calculation,the correlation coefficients are derived and combined to deal with the correlation problem caused by fanout reconvergence.The accuracy and scalability of the two methods are verified using three sets of approximate computing circuit instances and more circuits in Evo Approx8 b,which is an approximate computing circuit open source library.Experimental results show that relative to the Monte Carlo simulation,the two methods achieve average error rates of 0.46%and 1.29%and time overheads of 0.002%and 0.1%.Different from the existing approaches to reliability estimation for approximate computing circuits based on the original PTM model,the proposed methods reduce the space overheads by nearly 50%and achieve time overheads of 1.78%and 2.19%.