Research for radiation-hardened high-voltage SOI LDMOS

Based on the silicon-on-insulator(SOI) technology and radiation-hardened silicon gate(RSG) process, a radiation-hardened high-voltage lateral double-diffused MOSFET(LDMOS) device is presented in this paper. With the gate supply voltage of 30 V, the LDMOS device has a gate oxide thickness of 120 nm, and the RSG process is effective in reducing the total ionizing dose(TID) radiation-induced threshold voltage shift. The p-type ion implantation process and gate-enclosed layout topology are used to prevent radiation-induced leakage current through a parasitic path under the bird's beak and at the deep trench corner,and the device is compatible with high-voltage SOI CMOS process. In the proposed LDMOS, the total ionizing dose radiation degradation for the ON bias is more sensitive than the OFF bias. The experiment results show that the SOI LDMOS has a negative threshold voltage shift of 1.12 V, breakdown voltage of 135 V, and off-state leakage current of 0.92 pA/μm at an accumulated dose level of 100 krad(Si).

Reliability evaluation on sense-switch p-channel flash

In this paper,the reliability of sense-switch p-channel flash is evaluated extensively.The endurance result indicates that the p-channel flash could be programmed and erased for more than 10000 cycles;the room temperature read stress shows negligible influence on the p-channel flash cell;high temperature data retention at 150℃ is extrapolated to be about 5 years and 53 years corresponding to 30% and 40% degradation in the drive current,respectively.Moreover,the electrical parameters of the p-channel flash at different operation temperature are found to be less affected.All the results above indicate that the sense-switch p-channel flash is suitable to be used as the configuration cell in flash-based FPGA.

Design of GGNMOS ESD protection device for radiationhardened 0.18 μm CMOS process

In this paper,the ESD discharge capability of GGNMOS(gate grounded NMOS)device in the radiation-hardened 0.18μm bulk silicon CMOS process(Rad-Hard by Process:RHBP)is optimized by layout and ion implantation design.The effects of gate length,DCGS and ESD ion implantation of GGNMOS on discharge current density and lattice temperature are studied by TCAD and device simulation.The size of DCGS,multi finger number and single finger width of ESD verification structures are designed,and the discharge capacity and efficiency of GGNMOS devices in ESD are characterized by TLP test technology.Finally,the optimized GGNMOS is verified on the DSP circuit,and its ESD performance is over 3500 V in HBM mode.