Efficient and selective recovery of Ni, Cu, and Co from low-nickel matte via a hydrometallurgical process

Low-nickel matte was intensively characterized,and Ni,Cu,and Co were determined to exist mainly as(Fe,Ni)_9S_8 and Fe Ni_3,Cu_5FeS_4,and(Fe,Ni)_9S_8 and Fe_3O_4(in isomorphic form),respectively.The efficient and selective extraction of Ni,Cu,and Co from the low-nickel matte in an(NH_4)_2S_2O_8/NH_3·H_2O solution system was studied.The effects of(NH_4)_2S_2O_8 and NH_3·H_2O concentrations,leaching time,and leaching temperature on the metal extraction efficiency were systematically investigated.During the oxidative ammonia leaching process,the metal extraction efficiencies of Ni 81.07%,Cu 93.81%,and Co 71.74% were obtained under the optimal conditions.The relatively low leaching efficiency of Ni was mainly ascribed to Ni Fe alloy deactivation in ammonia solution.By introducing an acid pre-leaching process into the oxidative ammonia leaching process,we achieved the high extraction efficiencies of 98.03%,99.13%,and 85.60% for the valuable metals Ni,Cu,and Co,respectively,from the low-nickel matte.

Design for Low Power Testing of Computation Modules with Contiguous Subspace in VLSI

A kind of pseudo Gray code presentation of test patterns based on accumulation generators is presented and a low power test scheme is proposed to test computational function modules with contiguous subspace in very large scale integration （VLSI）, especially in digital signal processors （DSP）. If test patterns from accumulators for the modules are encoded in the pseudo Gray code presentation, the switching activities of the modules are reduced, and the decrease of the test power consumption is resulted in. Results of experimentation based on FPGA show that the test approach can reduce dynamic power consumption by an average of 17.40% for 8-bit ripple carry adder consisting of 3-2 counters. Then implementation of the low power test in hardware is exploited. Because of the reuse of adders, introduction of additional XOR logic gates is avoided successfully. The design minimizes additional hardware overhead for test and needs no adjustment of circuit structure. The low power test can detect any combinational stuck-at fault within the basic building block without any degradation of original circuit performance.