车用仪表背光灯的LED线性恒流驱动电路设计

阐述了可用于车用仪表背光灯的高精度LED线性恒流驱动芯片设计,重点讨论在设计并联方式LED线性恒流驱动电路时如何消除连线分布电阻的影响,并推出一种新颖的可消除连线分布电阻影响的电路,最终通过电路模拟测试加以验证。研究结果表明,在设计高精度、高稳定性、大电流、并联方式LED线性恒流驱动电路时,消除连线分布电阻影响很有必要。

Design of 32 kbit one-time programmable memory for microcontroller units

A 32 kbit OTP(one-time programmable)memory for MCUs(micro-controller units)used in remote controllers was designed.This OTP memory is used for program and data storage.It is required to apply 5.5V to BL(bit-line)and 11V to WL(word-line)for a OTP cell of 0.35μm ETOX(EEPROM tunnel oxide)type by MagnaChip.We use 5V transistors on column data paths to reduce the area of column data paths since they require small areas.In addition,we secure device reliability by using HV(high-voltage)transistors in the WL driver.Furthermore,we change from a static logic to a dynamic logic used for the WL driver in the core circuit.Also,we optimize the WD(write data)switch circuit.Thus,we can implement them with a small-area design.In addition,we implement the address predecoder with a small-area logic circuit.The area of the designed 32 kbit OTP with 5V and HV devices is 674.725μm×258.75μm(=0.1745mm2)and is 56.3% smaller than that using 3.3V devices.

Design of an 8 bit differential paired eFuse OTP memory IP reducing sensing resistance

For the conventional single-ended eFuse cell,sensing failures can occur due to a variation of a post-program eFuse resistance during the data retention time and a relatively high program resistance of several kilo ohms.A differential paired eFuse cell is designed which is about half the size smaller in sensing resistance of a programmed eFuse link than the conventional single-ended eFuse cell.Also,a sensing circuit of sense amplifier is proposed,based on D flip-flop structure to implement a simple sensing circuit.Furthermore,a sensing margin test circuit is proposed with variable pull-up loads out of consideration for resistance variation of a programmed eFuse.When an 8 bit eFuse OTP IP is designed with 0.18 μm standard CMOS logic of TSMC,the layout dimensions are 229.04 μm× 100.15 μm.All the chips function successfully when 20 test chips are tested with a program voltage of 4.2 V.

Design of small-area and high-efficiency DC-DC converter for 1 T SRAM

The direct current-direct current (DC-DC) converter is designed for 1 T static random access memory (SRAM) used in display driver integrated circuits (ICs), which consists of positive word-line voltage (VPWL), negative word-line voltage (VNWL) and half-VDD voltage (VHDD) generator. To generate a process voltage temperature (PVT)-insensitive VPWL and VNWL, a set of circuits were proposed to generate reference voltages using bandgap reference current generators for respective voltage level detectors. Also, a VPWL regulator and a VNWL charge pump were proposed for a small-area and low-power design. The proposed VPWL regulator can provide a large driving current with a small area since it regulates an input voltage (VCI) from 2.5 to 3.3 V. The VNWL charge pump can be implemented as a high-efficiency circuit with a small area and low power since it can transfer pumped charges to VNWL node entirely. The DC-DC converter for 1 T SRAM were designed with 0.11 μm mixed signal process and operated well with satisfactory measurement results.

Design of 32-bit differential paired eFuse OTP memory in a form of two-dimensional array

A differential paired eFuse OTP(one-time programmable)memory cell which can be configured into a 2D(two-dimensional)eFuse cell array was proposed.The sensible resistance of a programmed eFuse link is a half smaller than that of the single-ended counterpart and BL datum can be sensed without a reference voltage.With this 2D array of differential paired eFuse OTP memory cells,we design a 32-bit eFuse OTP memory IP.We use a sense amplifier based D F/F circuit as the BL(bit-line)SA(sense amplifier)and design a sensing margin test circuit with a variable pull-up load.It is confirmed by the function test that the designed 32-bit OTP memory IP functions normally on 30 sample dies.

Design of 256 bit single-poly MTP memory based on BCD process

We propose a single-poly MTP(multi-time programmable)cell consisting of one capacitor and two transistors based on MagnaChip's BCD process.The area of a unit cell is 37.743 75μm2.The proposed single-poly MTP cell is erased and programmed by the FN tunnelling scheme.We design a 256 bit MTP memory for PMICs(power management ICs)using the proposed single-poly MTP cells.For small-area designs,we propose a selection circuit between V10V and V5V,and a WL(word-line)driver by simplifying its logic circuit.We reduce the total layout area by using pumped internal node voltages from a seven-stage cross-coupled charge pump for V10V(=10V)and V5V(=5V)without any additional charge pumps.The layout size of the designed 256 bit MTP memory is 618.250μm×437.425μm.

Design of 512-bit logic process-based single poly EEPROM IP

A single poly EEPROM cell circuit sharing the deep N-well of a cell array was designed using the logic process. The proposed cell is written by the FN tunneling scheme and the cell size is 41.26 μm2, about 37% smaller than the conventional cell. Also, a small-area and low-power 512-bit EEPROM IP was designed using the proposed cells which was used for a 900 MHz passive UHF RFID tag chip. To secure the operation of the cell proposed with 3.3 V devices and the reliability of the used devices, an EEPROM core circuit and a DC-DC converter were proposed. Simulation results for the designed EEPROM IP based on the 0.18 μm logic process show that the power consumptions in read mode, program mode and erase mode are 11.82, 25.15, and 24.08 μW, respectively, and the EEPROM size is 0.12 mm2.