Time-domain analysis methodology for large-scale RLC circuits and its applications

With soaring work frequency and decreasing feature sizes, VLSI circuits with RLC parasitic components are more like analog circuits and should be carefully analyzed in physical design. However, the number of extracted RLC components is typically too large to be analyzed efficiently by using present analog circuit simulators like SPICE. In order to speedup the simulations without error penalty, this paper proposes a novel methodology to compress the time-descritized circuits resulted from numerical integration approximation at every time step. The main contribution of the methodology is the efficient structure-level compression of DC circuits containing many current sources, which is an important complement to present circuit analysis theory. The methodology consists of the following parts： 1） An approach is proposed to delete all intermediate nodes of RL branches. 2） An efficient approach is proposed to compress and back-solve parallel and serial branches so that it is error-free and of linear complexity to analyze circuits of tree topology. 3） The Y to πtransformation method is used to error-free reduce and back-solve the intermediate nodes of ladder circuits with the linear complexity. Thus, the whole simulation method is very accurate and of linear complexity to analyze circuits of chain topology. Based on the methodology, we propose several novel algorithms for efficiently solving RLC-model transient power/ground （P/G） networks. Among them, EQU-ADI algorithm of linear-complexity is proposed to solve RLC P/G networks with mesh-tree or mesh-chain topologies. Experimental results show that the proposed method is at least two orders of magnitude faster than SPICE while it can scale linearly in both time- and memory-complexity to solve very large P/G networks.

Reliable buffered clock tree routing algorithm with process variation tolerance

When IC technology is scaled into the very deep sub-micron regime, the optical proximity effects （OPE） turn into noticeable in optical lithography. Consequently, clock skew becomes more and more susceptible to process variations, such as OPE. In this paper, we propose a new buffered clock tree routing algorithm to prevent the influence of OPE and process variations to clock skew. Based on the concept of BSF （branch sensitivity factor）, our algorithm manages to reduce the skew sensitivity of the clock tree in the topology generation. The worst case skew due to the wire width change has been estimated, and proper buffers are inserted to avoid large capacitance load. Experimental results show that our algorithm can produce a more reliable, processinsensitive clock tree, and control clock skews in their permissible range evidently.

A single layer zero skew clock routing in X architecture

With its advantages in wirelength reduction and routing flexibility compared with conventional Manhattan routing, X architecture has been proposed and applied to modern IC design. As a critical part in high-performance integrated circuits, clock network design meets great challenges due to feature size decrease and clock frequency increase. In order to eliminate the delay and attenuation of clock signal introduced by the vias, and to make it more tolerant to process variations, in this paper, we propose an algorithm of a single layer zero skew clock routing in X architecture （called Pianar-CRX）. Our Planar- CRX method integrates the extended deferred-merge embedding algorithm （DME-X, which extends the DME algorithm to X architecture） with modified Ohtsuki＇s line-search algorithm to minimize the total wirelength and the bends. Compared with planar clock routing in the Manhattan plane, our method achieves a reduction of 6.81% in total wirelength on average and gets the resultant clock tree with fewer bends. Experimental results also indicate that our solution can be comparable with previous non-planar zero skew clock routing algorithm.