We present photonics technology based on a bulk-Si substrate for cost-sensitive dynamic random-access memory(DRAM)optical interface application.We summarize the progress on passive and active photonic devices using a ...We present photonics technology based on a bulk-Si substrate for cost-sensitive dynamic random-access memory(DRAM)optical interface application.We summarize the progress on passive and active photonic devices using a local-crystallized Si waveguide fabricated by solid phase epitaxy or laser-induced epitaxial growth on bulk-Si substrate.The process of integration of a photonic integrated circuit(IC)with an electronic IC is demonstrated using a 65 nm DRAM periphery process on 300 mm wafers to prove the possibility of seamless integration with various complementary metal-oxide-semiconductor devices.Using the bulk-Si photonic devices,we show the feasibility of high-speed multidrop interface:the Mach–Zehnder interferometer modulators and commercial photodetectors are used to demonstrate four-drop link operation at 10 Gb∕s,and the transceiver chips with photonic die and electronic die work for the DDR3 DRAM interface at 1.6 Gb∕s under a 1∶4 multidrop configuration.展开更多
文摘We present photonics technology based on a bulk-Si substrate for cost-sensitive dynamic random-access memory(DRAM)optical interface application.We summarize the progress on passive and active photonic devices using a local-crystallized Si waveguide fabricated by solid phase epitaxy or laser-induced epitaxial growth on bulk-Si substrate.The process of integration of a photonic integrated circuit(IC)with an electronic IC is demonstrated using a 65 nm DRAM periphery process on 300 mm wafers to prove the possibility of seamless integration with various complementary metal-oxide-semiconductor devices.Using the bulk-Si photonic devices,we show the feasibility of high-speed multidrop interface:the Mach–Zehnder interferometer modulators and commercial photodetectors are used to demonstrate four-drop link operation at 10 Gb∕s,and the transceiver chips with photonic die and electronic die work for the DDR3 DRAM interface at 1.6 Gb∕s under a 1∶4 multidrop configuration.
