在对新一代高效视频编码(High Efficiency Video Coding,HEVC)帧内预测Planar和DC模式算法分析的基础上,分别提出了高效的超大规模集成电路(Very Large Scale Integration Circuit,VLSI)设计方案,旨在解决处理延时较长、资源占用较大的...在对新一代高效视频编码(High Efficiency Video Coding,HEVC)帧内预测Planar和DC模式算法分析的基础上,分别提出了高效的超大规模集成电路(Very Large Scale Integration Circuit,VLSI)设计方案,旨在解决处理延时较长、资源占用较大的问题。针对Planar模式,提出一种在重组、合并算法的基础上,预测块复用的架构;针对DC模式,提出一种dcValue计算和滤波的基本块分离、各自复用不同块的架构。实验结果表明:所提架构与其他两种同类型架构相比,Planar模式实现平均处理延时减少了21%,资源消耗分别减少了14.7%和7%;DC模式实现平均处理延时减少了55%,同时资源消耗减少了22%和15%,能够满足1 920×1 080@30 f/s视频序列实时编码的需求。展开更多
优化台址风环境对提高大口径、高精度射电望远镜在中高频段的有效观测时长具有重要意义。通过风障调控风场可以有效减小风荷载对望远镜的影响。风障的布局设计除了与风障高度、孔隙率等参量有关外,还要综合考虑台址地形对挡风效率的影...优化台址风环境对提高大口径、高精度射电望远镜在中高频段的有效观测时长具有重要意义。通过风障调控风场可以有效减小风荷载对望远镜的影响。风障的布局设计除了与风障高度、孔隙率等参量有关外,还要综合考虑台址地形对挡风效率的影响。以奇台射电望远镜(QiTai radio Telescope,QTT)台址为研究对象,开展不同地形对风场调控影响的数值模拟研究。仿真结果表明,无风障时望远镜区的风速大小主要与上下游边界地形的最高海拔有关;布设风障时,若望远镜区域为水平地形,风障遮蔽区降低风速的大小与上游入流风攻角以及下游地形的海拔高度有关;台址实际斜坡地形增加了流场的复杂程度,在进行风障风场仿真时,上游边界要尽量延伸到相对较高山体的外围。不同边界地形的仿真结果表明,望远镜区风速折减效率差值最大达到6%。该研究可以为望远镜台址风场调控仿真中的地形建模提供可靠的参考。展开更多
Computer vision(CV)is widely expected to be the next big thing in emerging applications.So many heterogeneous architectures for computer vision emerge.However,plenty of data need to be transferred between different st...Computer vision(CV)is widely expected to be the next big thing in emerging applications.So many heterogeneous architectures for computer vision emerge.However,plenty of data need to be transferred between different structures for heterogeneous architecture.The long data transfer delay becomes the mainly problem to limit the processing speed for computer vision applications.For reducing data transfer delay and fasting computer vision applications,a clustered data-driven array processor is proposed.A three-level pipelining processing element is designed which supports two-buffer data flow interface and 8 bits,16 bits,32 bits subtext parallel computation.At the same time,for accelerating transcendental function computation,a four-way shared pipelining transcendental function accelerator is designed,which is based on Y-intercept adjusted piecewise linear segment algorithm.A distributed shared memory structure based on unified addressing is also employed.To verify efficiency of architecture,some image processing algorithms are implemented on proposed architecture.Simultaneously the proposed architecture has been implemented on Xilinx ZC 706 development board.The same circuitry has been synthesized using SMIC 130 nm CMOS technology.The circuitry is able to run at 100 MHz.Area is 26.58 mm2.展开更多
文摘优化台址风环境对提高大口径、高精度射电望远镜在中高频段的有效观测时长具有重要意义。通过风障调控风场可以有效减小风荷载对望远镜的影响。风障的布局设计除了与风障高度、孔隙率等参量有关外,还要综合考虑台址地形对挡风效率的影响。以奇台射电望远镜(QiTai radio Telescope,QTT)台址为研究对象,开展不同地形对风场调控影响的数值模拟研究。仿真结果表明,无风障时望远镜区的风速大小主要与上下游边界地形的最高海拔有关;布设风障时,若望远镜区域为水平地形,风障遮蔽区降低风速的大小与上游入流风攻角以及下游地形的海拔高度有关;台址实际斜坡地形增加了流场的复杂程度,在进行风障风场仿真时,上游边界要尽量延伸到相对较高山体的外围。不同边界地形的仿真结果表明,望远镜区风速折减效率差值最大达到6%。该研究可以为望远镜台址风场调控仿真中的地形建模提供可靠的参考。
基金the National Natural Science Foundation of China(No.61802304,61834005,61772417,61634004,61602377)Shaanxi Provincial Co-ordination Innovation Project of Science and Technology(No.2016KTZDGY02-04-02)+1 种基金Shaanxi Provincial Key R&D Plan(No.2017GY-060)Shaanxi International Science and Technology Cooperation Program(No.2018KW-006).
文摘Computer vision(CV)is widely expected to be the next big thing in emerging applications.So many heterogeneous architectures for computer vision emerge.However,plenty of data need to be transferred between different structures for heterogeneous architecture.The long data transfer delay becomes the mainly problem to limit the processing speed for computer vision applications.For reducing data transfer delay and fasting computer vision applications,a clustered data-driven array processor is proposed.A three-level pipelining processing element is designed which supports two-buffer data flow interface and 8 bits,16 bits,32 bits subtext parallel computation.At the same time,for accelerating transcendental function computation,a four-way shared pipelining transcendental function accelerator is designed,which is based on Y-intercept adjusted piecewise linear segment algorithm.A distributed shared memory structure based on unified addressing is also employed.To verify efficiency of architecture,some image processing algorithms are implemented on proposed architecture.Simultaneously the proposed architecture has been implemented on Xilinx ZC 706 development board.The same circuitry has been synthesized using SMIC 130 nm CMOS technology.The circuitry is able to run at 100 MHz.Area is 26.58 mm2.
