A rally integrated receiver RF front-end that meets WCDMA/GSM system requirements is presented.It supports SAW-less operation for WCDMA.To improve the linearity in terms of both IP3 and IP2,the RF front-end is compris...A rally integrated receiver RF front-end that meets WCDMA/GSM system requirements is presented.It supports SAW-less operation for WCDMA.To improve the linearity in terms of both IP3 and IP2,the RF front-end is comprised of multiple-gated LNAs with capacitive desensitization,current-mode passive mixers with the proposed IP2 calibration circuit and reconfigurable Tow-Thomas-like biquad TIAs.A new power-saving multi-mode divider with low phase noise is proposed to provide the 4-phase 25%-duty-cycle LO.In addition,a constant-g_m biasing with an on-chip resistor is adopted to make the conversion gain invulnerable to the process and temperature variations of the transimpedance.This RF front-end is integrated in a receiver with an on-chip frequency synthesizer in 0.13μm CMOS.The measurement results show that owing to this high-linearity RF front-end,the receiver achieves -6 dBm IIP3 and better than ＋60 dBm IIP2 for all modes and bands.展开更多
A fourth-order continuous-time sigma delta modulator with 20-MHz bandwidth, implemented in 130- nm CMOS technology is presented. The modulator is comprised of an active-RC operational-amplifier based loop filter, a 4-...A fourth-order continuous-time sigma delta modulator with 20-MHz bandwidth, implemented in 130- nm CMOS technology is presented. The modulator is comprised of an active-RC operational-amplifier based loop filter, a 4-bit internal quantizer and three current steering feedback DACs. A three-stage amplifier with low power is designed to satisfy the requirement of high dc gain and high gain-bandwidth product of the loop filter. Non-return- to-zero DAC pulse shaping is utilized to reduce clock jitter sensitivity. A special layout technique guarantees that the main feedback DAC reaches 12-bit match accuracy, avoiding the use of a dynamic element matching algorithm to induce excess loop delay. The experimental results demonstrate a 64.6-dB peak signal-to-noise ratio, and 66-dB dynamic range over a 20-MHz signal bandwidth when clocked at 480 MHz with 18-mW power consumption from a 1.2-V supply.展开更多
A low-phase-noise E-A fractional-N frequency synthesizer for GSM/PCS/DCS/WCDMA transceivers is presented. The voltage controlled oscillator is designed with a modified digital controlled capacitor array to extend the ...A low-phase-noise E-A fractional-N frequency synthesizer for GSM/PCS/DCS/WCDMA transceivers is presented. The voltage controlled oscillator is designed with a modified digital controlled capacitor array to extend the tuning range and minimize phase noise. A high-resolution adaptive frequency calibration technique is introduced to automatically choose frequency bands and increase phase-noise immunity. A prototype is implemented in 0.13 #m CMOS technology. The experimental results show that the designed 1.2 V wideband frequency synthesizer is locked from 3.05 to 5.17 GHz within 30 μs, which covers all five required frequency bands. The measured in-band phase noise are -89, -95.5 and -101 dBc/Hz for 3.8 GHz, 2 GHz and 948 MHz carriers, respectively, and accordingly the out-of-band phase noise are -121, -123 and -132 dBc/Hz at 1 MHz offset, which meet the phase-noise-mask requirements of the above-mentioned standards.展开更多
A 1500 mA,10 MHz self-adaptive on-time （SOT） controlled buck DC-DC converter is presented. Both a low-cost ripple compensation scheme （RCS） and a self-adaptive on-time generator （SAOTG） are proposed to solve the...A 1500 mA,10 MHz self-adaptive on-time （SOT） controlled buck DC-DC converter is presented. Both a low-cost ripple compensation scheme （RCS） and a self-adaptive on-time generator （SAOTG） are proposed to solve the system stability and frequency variation problem. Meanwhile a self-adaptive power transistor sizing （SAPTS） technique is used to optimize the efficiency especially with a heavy load. The circuit is implemented in a 2P4M 0.35μm CMOS process. A small external inductor of 0.47 μH and a capacitor of 4.7 μF are used to lower the cost of the converter and keep the output ripple to less than 10 mV. The measurement results show that the overshoot of the load transient response is 8 mV @ 200 mA step and the dynamic voltage scaling （DVS） performance is a rise of 16/zs/V and a fall of 20 μs/V. With a SAPTS technique and PFM control, the efficiency is maintained at more than 81% for a load range of 20 to 1500 mA and the peak efficiency reaches 88.43%.展开更多
A wideband variable gain amplifier （VGA） implemented in 0.13 μm CMOS technology is presented. To optimize noise performance, an active feedback amplifier with 15 dB fixed gain is put in the front, followed by modif...A wideband variable gain amplifier （VGA） implemented in 0.13 μm CMOS technology is presented. To optimize noise performance, an active feedback amplifier with 15 dB fixed gain is put in the front, followed by modified Cherry-Hooper amplifiers in cascade providing variable gain, which adopt dual loop feedback for band- width extension. Negative capacitive neutralization and capacitive source degeneration are employed for Miller effect compensation and DC offset cancellation, respectively. Measurement results show that the proposed VGA achieves a 35 dB gain tuning range with an upper 3-dB bandwidth larger than 3 GHz and the input 1 dB compression point of-29 dBm at the lowest gain state, while the minimum noise figure is 9 dB at the highest gain state. The core VGA （without test buffer） consumes 32 mW from 1.2 V power supply and occupies 0.48 mm2 area.展开更多
基金supported by the National Science and Technology Major Project of China(No.2009ZX01031-003-002)the National High Technology Research and Development Program of China(No.2009AA011605)
文摘A rally integrated receiver RF front-end that meets WCDMA/GSM system requirements is presented.It supports SAW-less operation for WCDMA.To improve the linearity in terms of both IP3 and IP2,the RF front-end is comprised of multiple-gated LNAs with capacitive desensitization,current-mode passive mixers with the proposed IP2 calibration circuit and reconfigurable Tow-Thomas-like biquad TIAs.A new power-saving multi-mode divider with low phase noise is proposed to provide the 4-phase 25%-duty-cycle LO.In addition,a constant-g_m biasing with an on-chip resistor is adopted to make the conversion gain invulnerable to the process and temperature variations of the transimpedance.This RF front-end is integrated in a receiver with an on-chip frequency synthesizer in 0.13μm CMOS.The measurement results show that owing to this high-linearity RF front-end,the receiver achieves -6 dBm IIP3 and better than ＋60 dBm IIP2 for all modes and bands.
基金Project Supported by the Important National Science & Technology Specific Projects of China(No.2009ZXO1O31-003-002)the State Key Laboratory Project of China(No.11MS002)
文摘A fourth-order continuous-time sigma delta modulator with 20-MHz bandwidth, implemented in 130- nm CMOS technology is presented. The modulator is comprised of an active-RC operational-amplifier based loop filter, a 4-bit internal quantizer and three current steering feedback DACs. A three-stage amplifier with low power is designed to satisfy the requirement of high dc gain and high gain-bandwidth product of the loop filter. Non-return- to-zero DAC pulse shaping is utilized to reduce clock jitter sensitivity. A special layout technique guarantees that the main feedback DAC reaches 12-bit match accuracy, avoiding the use of a dynamic element matching algorithm to induce excess loop delay. The experimental results demonstrate a 64.6-dB peak signal-to-noise ratio, and 66-dB dynamic range over a 20-MHz signal bandwidth when clocked at 480 MHz with 18-mW power consumption from a 1.2-V supply.
基金Project supported by the National High Technology Research and Development Program of China(No.2009AA011605)
文摘A low-phase-noise E-A fractional-N frequency synthesizer for GSM/PCS/DCS/WCDMA transceivers is presented. The voltage controlled oscillator is designed with a modified digital controlled capacitor array to extend the tuning range and minimize phase noise. A high-resolution adaptive frequency calibration technique is introduced to automatically choose frequency bands and increase phase-noise immunity. A prototype is implemented in 0.13 #m CMOS technology. The experimental results show that the designed 1.2 V wideband frequency synthesizer is locked from 3.05 to 5.17 GHz within 30 μs, which covers all five required frequency bands. The measured in-band phase noise are -89, -95.5 and -101 dBc/Hz for 3.8 GHz, 2 GHz and 948 MHz carriers, respectively, and accordingly the out-of-band phase noise are -121, -123 and -132 dBc/Hz at 1 MHz offset, which meet the phase-noise-mask requirements of the above-mentioned standards.
文摘A 1500 mA,10 MHz self-adaptive on-time （SOT） controlled buck DC-DC converter is presented. Both a low-cost ripple compensation scheme （RCS） and a self-adaptive on-time generator （SAOTG） are proposed to solve the system stability and frequency variation problem. Meanwhile a self-adaptive power transistor sizing （SAPTS） technique is used to optimize the efficiency especially with a heavy load. The circuit is implemented in a 2P4M 0.35μm CMOS process. A small external inductor of 0.47 μH and a capacitor of 4.7 μF are used to lower the cost of the converter and keep the output ripple to less than 10 mV. The measurement results show that the overshoot of the load transient response is 8 mV @ 200 mA step and the dynamic voltage scaling （DVS） performance is a rise of 16/zs/V and a fall of 20 μs/V. With a SAPTS technique and PFM control, the efficiency is maintained at more than 81% for a load range of 20 to 1500 mA and the peak efficiency reaches 88.43%.
基金Project supported by the National High Technology Research and Development of China(No.2009AA01Z261)the State Key Laboratory of Wireless Telecommunication,Southeast University
文摘A wideband variable gain amplifier （VGA） implemented in 0.13 μm CMOS technology is presented. To optimize noise performance, an active feedback amplifier with 15 dB fixed gain is put in the front, followed by modified Cherry-Hooper amplifiers in cascade providing variable gain, which adopt dual loop feedback for band- width extension. Negative capacitive neutralization and capacitive source degeneration are employed for Miller effect compensation and DC offset cancellation, respectively. Measurement results show that the proposed VGA achieves a 35 dB gain tuning range with an upper 3-dB bandwidth larger than 3 GHz and the input 1 dB compression point of-29 dBm at the lowest gain state, while the minimum noise figure is 9 dB at the highest gain state. The core VGA （without test buffer） consumes 32 mW from 1.2 V power supply and occupies 0.48 mm2 area.
