A 5 Gb/s adaptive equalizer with a new adaptation scheme is presented here by using 0.13μm CMOS process. The circuit consists of the combination of equalizer amplifier, limiter amplifier and adaptation loop. The adap...A 5 Gb/s adaptive equalizer with a new adaptation scheme is presented here by using 0.13μm CMOS process. The circuit consists of the combination of equalizer amplifier, limiter amplifier and adaptation loop. The adaptive algorithm exploits both the low frequency gain loop and the equalizer loop to minimize the inter-symbol interference （ISI） for a variety of cable characteristics. In addition, an offset cancellation loop is used to alleviate the offset influence of the signal path. The adaptive equalizer core occupies an area of 0.3567 mm2 and consumes a power consumption of 81.7 mW with 1.8 V power supply. Experiment results demonstrate that the equalizer could compensate for a designed cable loss with 0.23 UI peak-to-peak jitter.展开更多
基金Project supported by the National Natural Science Foundation of China(No.61376099)the Foundation for Fundamental Research of China(No.JSZL2016110B003)the Major Fundamental Research Program of Shaanxi(No.2017ZDJC-26)
文摘A 5 Gb/s adaptive equalizer with a new adaptation scheme is presented here by using 0.13μm CMOS process. The circuit consists of the combination of equalizer amplifier, limiter amplifier and adaptation loop. The adaptive algorithm exploits both the low frequency gain loop and the equalizer loop to minimize the inter-symbol interference （ISI） for a variety of cable characteristics. In addition, an offset cancellation loop is used to alleviate the offset influence of the signal path. The adaptive equalizer core occupies an area of 0.3567 mm2 and consumes a power consumption of 81.7 mW with 1.8 V power supply. Experiment results demonstrate that the equalizer could compensate for a designed cable loss with 0.23 UI peak-to-peak jitter.
