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A Correntropy-based Affine Iterative Closest Point Algorithm for Robust Point Set Registration 被引量:7
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作者 hongchen chen Xie Zhang +2 位作者 Shaoyi Du Zongze Wu Nanning Zheng 《IEEE/CAA Journal of Automatica Sinica》 SCIE EI CSCD 2019年第4期981-991,共11页
The iterative closest point(ICP)algorithm has the advantages of high accuracy and fast speed for point set registration,but it performs poorly when the point set has a large number of noisy outliers.To solve this prob... The iterative closest point(ICP)algorithm has the advantages of high accuracy and fast speed for point set registration,but it performs poorly when the point set has a large number of noisy outliers.To solve this problem,we propose a new affine registration algorithm based on correntropy which works well in the affine registration of point sets with outliers.Firstly,we substitute the traditional measure of least squares with a maximum correntropy criterion to build a new registration model,which can avoid the influence of outliers.To maximize the objective function,we then propose a robust affine ICP algorithm.At each iteration of this new algorithm,we set up the index mapping of two point sets according to the known transformation,and then compute the closed-form solution of the new transformation according to the known index mapping.Similar to the traditional ICP algorithm,our algorithm converges to a local maximum monotonously for any given initial value.Finally,the robustness and high efficiency of affine ICP algorithm based on correntropy are demonstrated by 2D and 3D point set registration experiments. 展开更多
关键词 AFFINE ITERATIVE closest point(ICP)algorithm correntropy-based ROBUST POINT set REGISTRATION
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A9.8-30.1GHzCMOSlow-noise amplifier with a 3.2-dB noise figure using inductor-and transformer-based gm-boosting techniques
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作者 hongchen chen Haoshen ZHU +2 位作者 LiangWU Wenquan CHE Quan XUE 《Frontiers of Information Technology & Electronic Engineering》 SCIE EI CSCD 2021年第4期586-598,共13页
A 9.8–30.1 GHz CMOS low-noise amplifier(LNA)with a 3.2-dB minimum noise figure(NF)is presented.At the architecture level,a topology based on common-gate(CG)cascading with a common-source(CS)amplifier is proposed for ... A 9.8–30.1 GHz CMOS low-noise amplifier(LNA)with a 3.2-dB minimum noise figure(NF)is presented.At the architecture level,a topology based on common-gate(CG)cascading with a common-source(CS)amplifier is proposed for simultaneous wideband input matching and relatively high gain.At the circuit level,multiple techniques are proposed to improve LNA performance.First,in the CG stage,loading effect is properly used instead of the conventional feedback technique,to enable simultaneous impedance and noise matching.Second,based on in-depth theoretical analysis,the inductor-and transformer-based gm-boosting techniques are employed for the CG and CS stages,respectively,to enhance the gain and reduce power consumption.Third,the floating-body method,which was originally proposed to lower NF in CS amplifiers,is adopted in the CG stage to further reduce NF.Fabricated in a 65-nm CMOS technology,the LNA chip occupies an area of only 0.2 mm^(2)and measures a maximum power gain of 10.9 dB with−3 dB bandwidth from 9.8 to 30.1 GHz.The NF exhibits a minimum value of 3.2 dB at 15 GHz and is below 5.7 dB across the entire bandwidth.The LNA consumes 15.6 mW from a 1.2-V supply. 展开更多
关键词 CMOS gm-boosting Low-noise amplifier Transformer Common-gate
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