Carbon nanotube field-effect transistors(CNTFETs) are reliable alternatives for conventional transistors, especially for use in approximate computing(AC) based error-resilient digital circuits. In this paper, CNTFET t...Carbon nanotube field-effect transistors(CNTFETs) are reliable alternatives for conventional transistors, especially for use in approximate computing(AC) based error-resilient digital circuits. In this paper, CNTFET technology and the gate diffusion input(GDI) technique are merged, and three new AC-based full adders(FAs) are presented with 6, 6, and 8 transistors, separately. The nondominated sorting based genetic algorithm II(NSGA-II) is used to attain the optimal performance of the proposed cells by considering the number of tubes and chirality vectors as its variables. The results confirm the circuits' improvement by about 50% in terms of power-delay-product(PDP) at the cost of area occupation. The Monte Carlo method(MCM) and 32-nm CNTFET technology are used to evaluate the lithographic variations and the stability of the proposed circuits during the fabrication process, in which the higher stability of the proposed circuits compared to those in the literature is observed. The dynamic threshold(DT) technique in the transistors of the proposed circuits amends the possible voltage drop at the outputs. Circuitry performance and error metrics of the proposed circuits nominate them for the least significant bit(LSB) parts of more complex arithmetic circuits such as multipliers.展开更多
文摘Carbon nanotube field-effect transistors(CNTFETs) are reliable alternatives for conventional transistors, especially for use in approximate computing(AC) based error-resilient digital circuits. In this paper, CNTFET technology and the gate diffusion input(GDI) technique are merged, and three new AC-based full adders(FAs) are presented with 6, 6, and 8 transistors, separately. The nondominated sorting based genetic algorithm II(NSGA-II) is used to attain the optimal performance of the proposed cells by considering the number of tubes and chirality vectors as its variables. The results confirm the circuits' improvement by about 50% in terms of power-delay-product(PDP) at the cost of area occupation. The Monte Carlo method(MCM) and 32-nm CNTFET technology are used to evaluate the lithographic variations and the stability of the proposed circuits during the fabrication process, in which the higher stability of the proposed circuits compared to those in the literature is observed. The dynamic threshold(DT) technique in the transistors of the proposed circuits amends the possible voltage drop at the outputs. Circuitry performance and error metrics of the proposed circuits nominate them for the least significant bit(LSB) parts of more complex arithmetic circuits such as multipliers.
