SDRAM (Synchronous DRAM) has become the memory standard in many digital system designs, because of low price and high read/write speed. In this paper, Based on the analysis of the working principle and characteristics...SDRAM (Synchronous DRAM) has become the memory standard in many digital system designs, because of low price and high read/write speed. In this paper, Based on the analysis of the working principle and characteristics of SDRAM, an SDRAM controller design method is proposed based on field programmable logic gate array FPGA. In order to reduce resource consumption and increase the read and write speed of SDRAM, the performance control of SDRAM is further optimized. We designed SDRAM controller by using Verilog HDL and Altera Quartus II 14.1 software, and simulated about this design with Model Sim-Altera 10.3c software. Then we verified this design by using Cyclone V 5CSEMA5F31C6 FPGA in DE1-SoC development board. The verification results show that the SDRAM is initialized successfully, the input and output data are completely consistent, and it has stable refresh and read and write functions. The SDRAM controller design meets the requirements.展开更多
文摘SDRAM (Synchronous DRAM) has become the memory standard in many digital system designs, because of low price and high read/write speed. In this paper, Based on the analysis of the working principle and characteristics of SDRAM, an SDRAM controller design method is proposed based on field programmable logic gate array FPGA. In order to reduce resource consumption and increase the read and write speed of SDRAM, the performance control of SDRAM is further optimized. We designed SDRAM controller by using Verilog HDL and Altera Quartus II 14.1 software, and simulated about this design with Model Sim-Altera 10.3c software. Then we verified this design by using Cyclone V 5CSEMA5F31C6 FPGA in DE1-SoC development board. The verification results show that the SDRAM is initialized successfully, the input and output data are completely consistent, and it has stable refresh and read and write functions. The SDRAM controller design meets the requirements.
