This article presents a high speed third-order continuous-time(CT)sigma-delta analog-to-digital converter(SDADC)based on voltagecontrolled oscillator(VCO),featuring a digital programmable quantizer structure.To improv...This article presents a high speed third-order continuous-time(CT)sigma-delta analog-to-digital converter(SDADC)based on voltagecontrolled oscillator(VCO),featuring a digital programmable quantizer structure.To improve the overall performance,not only oversampling technique but also noise-shaping enhancing technique is used to suppress in-band noise.Due to the intrinsic first-order noise-shaping of the VCO quantizer,the proposed third-order SDADC can realize forth-order noise-shaping ideally.As a bright advantage,the proposed programmable VCO quantizer is digital-friendly,which can simplify the design process and improve antiinterference capability of the circuit.A 4-bit programmable VCO quantizer clocked at 2.5 GHz,which is proposed in a 40 nm complementary metaloxide semiconductor(CMOS)technology,consists of an analog VCO circuit and a digital programmable quantizer,achieving 50.7 dB signal-to-noise ratio(SNR)and 26.9 dB signal-to-noise-and-distortion ration(SNDR)for a 19 MHz−3.5 dBFS input signal in 78 MHz bandwidth(BW).The digital quantizer,which is programmed in the Verilog hardware description language(HDL),consists of two-stage D-flip-flop(DFF)based registers,XOR gates and an adder.The presented SDADC adopts the cascade of integrators with feed-forward summation(CIFF)structure with a third-order loop filter,operating at 2.5 GHz and showing behavioral simulation performance of 92.9 dB SNR over 78 MHz bandwidth.展开更多
基金This work was supported by the Natural Science Foundation of the Jiangsu Higher Education Institutions of China under Grant No.18KJB510045.
文摘This article presents a high speed third-order continuous-time(CT)sigma-delta analog-to-digital converter(SDADC)based on voltagecontrolled oscillator(VCO),featuring a digital programmable quantizer structure.To improve the overall performance,not only oversampling technique but also noise-shaping enhancing technique is used to suppress in-band noise.Due to the intrinsic first-order noise-shaping of the VCO quantizer,the proposed third-order SDADC can realize forth-order noise-shaping ideally.As a bright advantage,the proposed programmable VCO quantizer is digital-friendly,which can simplify the design process and improve antiinterference capability of the circuit.A 4-bit programmable VCO quantizer clocked at 2.5 GHz,which is proposed in a 40 nm complementary metaloxide semiconductor(CMOS)technology,consists of an analog VCO circuit and a digital programmable quantizer,achieving 50.7 dB signal-to-noise ratio(SNR)and 26.9 dB signal-to-noise-and-distortion ration(SNDR)for a 19 MHz−3.5 dBFS input signal in 78 MHz bandwidth(BW).The digital quantizer,which is programmed in the Verilog hardware description language(HDL),consists of two-stage D-flip-flop(DFF)based registers,XOR gates and an adder.The presented SDADC adopts the cascade of integrators with feed-forward summation(CIFF)structure with a third-order loop filter,operating at 2.5 GHz and showing behavioral simulation performance of 92.9 dB SNR over 78 MHz bandwidth.
